參數(shù)資料
型號(hào): PIC16C72T
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontrollers with A/D Converter
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器
文件頁數(shù): 47/124頁
文件大?。?/td> 1391K
代理商: PIC16C72T
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 47
8.4
SSP I
2
C Operation
The SSP module in I
2
C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifica-
tions as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 8-7:
SSP BLOCK DIAGRAM
(I
2
C MODE)
The SSP module has five registers for I
2
C operation.
These are the:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly acces-
sible
SSP Address Register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
I
2
C Slave mode (7-bit address)
I
2
C Slave mode (10-bit address)
I
2
C Slave mode (7-bit address), with start and
stop bit interrupts enabled
I
2
C Slave mode (10-bit address), with start and
stop bit interrupts enabled
I
2
C Firmware controlled master operation, slave
is idle
Selection of any I
2
C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I
2
C operation may be
found in the PICmicro Mid-Range MCU Reference
Manual, DS33023.
8.4.1
SLAVE MODE
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b)
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-3 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
Read
Write
SSPSR reg
Match detect
SSPADD reg
Start and
Stop bit detect
SSPBUF reg
Internal
data bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
SDI/
SDA
shift
clock
MSb
LSb
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