參數(shù)資料
型號: PIC16C72A-20I/ML
廠商: Microchip Technology
文件頁數(shù): 85/120頁
文件大小: 0K
描述: IC MCU OTP 2KX14 A/D PWM 28QFN
標準包裝: 61
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: OTP
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 5x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
其它名稱: PIC16C72A20I/ML
PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 67
11.0
INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 11-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 11-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
TABLE 11-1
OPCODE FIELD
DESCRIPTIONS
The instruction set is highly orthogonal and is grouped
into three basic categories:
Byte-oriented operations
Bit-oriented operations
Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1
s. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2
s.
Table 11-2 lists the instructions recognized by the
MPASM assembler.
Figure 11-1 shows the general formats that the instruc-
tions can have.
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 11-1: GENERAL FORMAT FOR
INSTRUCTIONS
A description of each instruction is available in the
PICmicro
Mid-Range
Reference
Manual,
(DS33023).
Field
Description
f
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
Z
Zero bit
DC
Digit Carry bit
C
Carry bit
Note:
To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTION and TRIS instructions.
Byte-oriented file register operations
13
8
7
6
0
d = 0 for destination W
OPCODE
d
f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
13
11
10
0
OPCODE
k (literal)
k = 11-bit immediate value
General
CALL
and GOTO instructions only
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