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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16C72-20/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 103/114闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 2KX14 A/D PWM 28SSOP |
| 鐢㈠搧鍩硅〒妯″锛� | Asynchronous Stimulus |
| 妯欐簴鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 6 V |
| 鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP |
| 鍏跺畠鍚嶇ū锛� | PIC16C72-20/SSR PIC16C72-20/SSR-ND |
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1997 Microchip Technology Inc.
DS30390E-page 89
PIC16C7X
11.4
I2C Overview
This section provides an overview of the Inter-Inte-
the operation of the SSP module in I2C mode.
The I2C bus is a two-wire serial interface developed by
the Philips Corporation. The original specication, or
standard mode, was for data transfers of up to 100
Kbps. The enhanced specication (fast mode) is also
supported. This device will communicate with both
standard and fast mode devices if attached to the same
bus. The clock will determine the data rate.
The I2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the 鈥渕aster鈥�
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the 鈥渟lave.鈥� All portions of the slave
protocol are implemented in the SSP module鈥檚 hard-
ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXX software. Table 11-3 denes some of the
I2C bus terminology. For additional information on the
I2C interface specication, refer to the Philips docu-
ment 鈥�
The I2C bus and how to use it.鈥� #939839340011,
which can be obtained from the Philips Corporation.
In the I2C interface protocol each device has an
address. When a master wishes to initiate a data trans-
fer, it rst transmits the address of the device that it
wishes to 鈥渢alk鈥� to. All devices 鈥渓(f膩)isten鈥� to see if this is
their address. Within this address, a bit species if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is they can be thought of as operating in either
of these two relations:
Master-transmitter and Slave-receiver
Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I2C bus is
limited only by the maximum bus loading specication
of 400 pF.
11.4.1
INITIATING AND TERMINATING DATA
TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is dened as a high
to low transition of the SDA when the SCL is high. The
STOP condition is dened as a low to high transition of
the SDA when the SCL is high. Figure 11-14 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the denition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE 11-14: START AND STOP
CONDITIONS
SDA
SCL
S
P
Start
Condition
Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
TABLE 11-3:
I2C BUS TERMINOLOGY
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
Applicable Devices
72 73 73A 74 74A 76 77
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| PIC16C72-04/SS | IC MCU OTP 2KX14 A/D PWM 28SSOP |
| PIC16C72/JW | IC MCU EPROM2KX14 A/D PWM 28CDIP |
| PIC16C711/JW | IC MCU EPROM 1KX14 A/D 18CDIP |
| SI2400-FS | IC ISOMODEM SYST-SIDE DAA 16SOIC |
| PIC16LC63-04/SO | IC MCU OTP 4KX14 PWM 28SOIC |
鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| PIC16C72A/JW | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72A-04/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72A-04/SP | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 3.5KB 128 RAM 22 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16C72A-04/SP | 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:IC 8BIT CMOS MCU 16C72 SDIL28 |
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