MSSP I2
參數(shù)資料
型號(hào): PIC16C717-E/P
廠商: Microchip Technology
文件頁數(shù): 197/220頁
文件大?。?/td> 0K
描述: IC MCU CMOS A/D 2K 20MHZ 18-DIP
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
其它名稱: PIC16C717E/P
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PIC16C717/770/771
DS41120B-page 76
Advance Information
2002 Microchip Technology Inc.
9.2
MSSP I2C Operation
The MSSP module in I2C mode fully implements all
master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine when the bus is free (multi-
master function). The MSSP module implements the
Standard mode specifications, as well as 7-bit and 10-
bit addressing.
Two pins are used to transfer data. They are the SCL
pin (clock) and the SDA pin (data). The MSSP module
functions are enabled by setting SSP Enable bit
SSPEN (SSPCON<5>). The SCL and SDA pins are
"glitch" filtered when operating as inputs. This filter
functions in both the 100 kHz and 400 kHz modes.
When these pins operate as outputs in the 100 kHz
mode, there is a slew rate control of the pin that is inde-
pendent of device frequency.
Before selecting any I2C mode, the SCL and SDA pins
must be programmed as inputs by setting the appropri-
ate TRIS bits. This allows the MSSP module to configure
and drive the I/O pins as required by the I2C protocol.
The MSSP module has six registers for I2C operation.
They are listed below.
SSP Control Register (SSPCON)
SSP Control Register2 (SSPCON2)
SSP STATUS Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
SSP Address Register (SSPADD)
The SSPCON register allows for control of the I2C
operation. Four mode selection bits (SSPCON<3:0>)
configure the MSSP as any one of the following I2C
modes:
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Master mode
SCL Freq = FOSC / [4
(SSPADD + 1)]
I2C Slave mode with START and STOP interrupts
(7-bit address)
I2C Slave mode with START and STOP interrupts
(10-bit address)
Firmware Controlled Master mode
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit. It specifies whether the
received byte was data or address, if the next byte is
the completion of 10-bit address, and if this will be a
read or write data transfer.
SSPBUF is the register to which the transfer data is
written, and from which the transfer data is read. The
SSPSR register shifts the data in or out of the device.
In receive operations, the SSPBUF and SSPSR create
a doubled, buffered receiver. This allows reception of
the next byte to begin before reading the last byte of
received data. When the complete byte is received, it is
transferred from the SSPSR register to the SSPBUF
register and flag bit SSPIF is set. If another complete
byte is received before the SSPBUF register is read a
receiver overflow occurs, in which case, the SSPOV bit
(SSPCON<6>) is set and the byte in the SSPSR is lost.
FIGURE 9-7:
I2C SLAVE MODE BLOCK
DIAGRAM
9.2.1
UPWARD COMPATIBILITY WITH
SSP MODULE
The MSSP module includes three SSP modes of oper-
ation to maintain upward compatibility with the SSP
module. These modes are:
Firmware controlled Master mode (slave idle)
7-bit Slave mode with START and STOP
condition interrupts.
10-bit Slave mode with START and STOP
condition interrupts.
The firmware controlled Master mode enables the
START and STOP condition interrupts but all other I2C
functions are generated through firmware including:
Generating the START and STOP conditions
Generating the SCL clock
Supplying the SDA bits in the proper time and
phase relationship to the SCL signal.
In firmware controlled Master mode, the SCL and SDA
lines are manipulated by clearing and setting the corre-
sponding TRIS bits. The output level is always low irre-
spective of the value(s) in the PORT register. A ‘1’ is
output by setting the TRIS bit and a ‘0’ is output by
clearing the TRIS bit
The 7-bit and 10-bit Slave modes with START and
STOP condition interrupts operate identically to the
MSSP Slave modes except that START and STOP
conditions generate SSPIF interrupts.
Read
Write
SSPSR reg
Match detect
SSPADD reg
START and
STOP bit detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, RESET
S, P bits
(SSPSTAT reg)
RB2/SCK/
Shift
Clock
MSb
LSb
SCL
RB4/SDI/
SDA
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