參數(shù)資料
型號: PIC16C711T-20E/SS
廠商: Microchip Technology
文件頁數(shù): 17/177頁
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D 20SSOP
標準包裝: 1,600
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: OTP
RAM 容量: 68 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉換器: A/D 4x8b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
113
7593L–AVR–09/12
AT90USB64/128
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
14.8.5
OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
14.8.6
TIMSK0 – Timer/Counter Interrupt Mask Register
Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits and will always read as zero.
Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Inter-
rupt Flag Register – TIFR0.
14.8.7
TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Bit
7
65
43
21
0
OCR0B[7:0]
OCR0B
Read/write
R/W
Initial value
00
Bit
7
6
543
2
1
0
OCIE0B
OCIE0A
TOIE0
TIMSK0
Read/write
R
R/W
Initial value
0
Bit
7654
32
10
––––
–OCF0B
OCF0A
TOV0
TIFR0
Read/write
RRRR
RR/W
R/W
Initial value
0000
00
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