參數(shù)資料
型號： PIC16C711T-20/SO
廠商： Microchip Technology
文件頁數(shù)： 96/177頁
文件大小： 0K
描述： IC MCU OTP 1KX14 A/D 18SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 1,100
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 1.75KB（1K x 14）
程序存儲器類型： OTP
RAM 容量： 68 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 18-SOIC（0.295"，7.50mm 寬）
包裝： 帶卷 (TR)
1997 Microchip Technology Inc.
DS30272A-page 25
PIC16C71X
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is a 5-bit latch.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers) which can congure
these pins as output or input.
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modied, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 5-1:
INITIALIZING PORTA
BCF
STATUS, RP0
;
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
BSF
STATUS, RP0
; Select Bank 1
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<4> as outputs
; TRISA<7:5> are always
; read as '0'.
Applicable Devices
710 71 711 715
Note:
On a Power-on Reset, these pins are con-
gured as analog inputs and read as '0'.
FIGURE 5-1:
BLOCK DIAGRAM OF
RA3:RA0 PINS
FIGURE 5-2:
BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data
bus
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
VSS
VDD
I/O pin(1)
Note 1:
I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
I/O pin(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
Q
D
Q
CK
Q
D
Q
CK
EN
Q
D
EN
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