![](http://datasheet.mmic.net.cn/260000/PIC16C710_datasheet_15942818/PIC16C710_133.png)
1996 Microchip Technology Inc.
DS30390D-page 133
PIC16C7X
14.5
Interrupts
Applicable Devices
710 71 711 72 73 73A 74 74A
The PIC16C7X family has up to 12 sources of interrupt:
Interrupt Sources
Applicable Devices
711
72
711
72
711
72
711
72
711
72
711
72
711
72
711
72
711
72
711
72
711
72
711
72
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
A/D Interrupt
TMR1 overflow interrupt
TMR2 matches period interrupt
CCP1 interrupt
CCP2 interrupt
USART Receive
USART Transmit
Synchronous serial port interrupt
Parallel slave port read/write interrupt
710
710
710
710
710
710
710
710
710
710
710
710
71
71
71
71
71
71
71
71
71
71
71
71
73
73
73
73
73
73
73
73
73
73
73
73
73A
73A
73A
73A
73A
73A
73A
73A
73A
73A
73A
74
74
74
74
74
74
74
74
74
74
74
74
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction,
RETFIE
, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
Note:
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
22). The latency is the same for one or two cycle
instructions. Individual interrupt flag bits are set regard-
less of the status of their corresponding mask bit or the
GIE bit.
Note:
For the PIC16C71/73/74
If an interrupt occurs while the Global Inter-
rupt Enable (GIE) bit is being cleared, the
GIE bit may unintentionally be re-enabled
by the user’s Interrupt Service Routine (the
RETFIE
instruction). The events that
would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged.
2.
The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
3.
The Interrupt Service Routine com-
pletes with the execution of the
RET-
FIE
instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF INTCON, GIE ; Disable global
; interrupt bit
BTFSC INTCON, GIE ; Global interrupt
; disabled
GOTO LOOP ; NO, try again
: ; Yes, continue
; with program
; flow