80h(1) INDF Addressing this location us" />
參數(shù)資料
型號: PIC16C67-20/P
廠商: Microchip Technology
文件頁數(shù): 47/126頁
文件大?。?/td> 0K
描述: IC MCU OTP 8KX14 PWM 40DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
配用: 444-1001-ND - DEMO BOARD FOR PICMICRO MCU
1997 Microchip Technology Inc.
DS30234D-page 27
PIC16C6X
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h
Unimplemented
89h
Unimplemented
8Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
8Ch
PIE1
(5)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
8Dh
PIE2
CCP2IE
---- ---0
8Eh
PCON
POR
BOR
---- --qq
---- --uu
8Fh
Unimplemented
90h
Unimplemented
91h
Unimplemented
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
D/A
P
S
R/W
UA
BF
--00 0000
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
98h(2)
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
99h(2)
SPBRG
Baud Rate Generator Register
0000 0000
9Ah
Unimplemented
9Bh
Unimplemented
9Ch
Unimplemented
9Dh
Unimplemented
9Eh
Unimplemented
9Fh
Unimplemented
TABLE 4-3:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
These registers can be addressed from either bank.
2:
The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3:
Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4:
The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.
5:
PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.
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