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  • 參數(shù)資料
    型號: PIC16C65A-20I/PQ
    廠商: Microchip Technology
    文件頁數(shù): 92/126頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 4KX14 PWM 44-MQFP
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    標準包裝: 96
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: I²C,SPI,UART/USART
    外圍設備: 欠壓檢測/復位,POR,PWM,WDT
    輸入/輸出數(shù): 33
    程序存儲器容量: 7KB(4K x 14)
    程序存儲器類型: OTP
    RAM 容量: 192 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-QFP
    包裝: 托盤
    配用: 309-1002-ND - ADAPTER 44-PQFP TO 40-DIP
    68
    AT90S/LS4433
    1042H–AVR–04/03
    ADC Multiplexer Select
    Register – ADMUX
    Bit 7 – Res: Reserved Bit
    This bit is a reserved bit in the AT90S4433, and should be written to zero if accessed.
    Bit 6 – ADCBG: ADC Bandgap Select
    When this bit is set and the BOD is enabled (BODEN Fuse is programmed), a fixed
    bandgap voltage of 1.22V ± 0.1V replaces the normal input to the ADC. When this bit is
    cleared, the normal input pin (as selected by MUX2..MUX0) is applied to the ADC.
    Bits 5..3 – Res: Reserved Bits
    These bits are reserved bits in the AT90S4433, and should be written to zero if
    accessed.
    Bits 2..0 – MUX2..MUX0: Analog Channel Select Bits 2 - 0
    The value of these three bits selects which analog input 5 - 0 is connected to the ADC.
    ADC Control and Status
    Register – ADCSR
    Bit 7 – ADEN: ADC Enable
    Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is
    turned off. Turning the ADC off while a conversion is in progress will terminate this
    conversion.
    Bit 6 – ADSC: ADC Start Conversion
    In Single Conversion mode, a logical “1” must be written to this bit to start each conver-
    sion. In Free Run mode, a logical “1” must be written to this bit to start the first
    conversion. The first time ADSC has been written after the ADC has been enabled, or if
    ADSC is written at the same time as the ADC is enabled, a dummy conversion will pre-
    cede the initiated conversion. This dummy conversion performs initialization of the ADC.
    ADSC remains high during the conversion. ADSC goes low after the conversion is com-
    plete, but before the result is written to the ADC Data Registers. This allows a new
    conversion to be initiated before the current conversion is complete. The new conver-
    sion will then start immediately after the current conversion completes. When a dummy
    conversion precedes a real conversion, ADSC will stay high until the real conversion
    completes.
    Writing a “0” to this bit has no effect.
    Bit
    7
    6
    543
    210
    $07 ($27)
    ADCBG
    MUX2
    MUX1
    MUX0
    ADMUX
    Read/Write
    R
    R/W
    R
    R/W
    Initial Value
    0
    Bit
    7654
    321
    0
    $06 ($26)
    ADEN
    ADSC
    ADFR
    ADIF
    ADIE
    ADPS2
    ADPS1
    ADPS0
    ADCSR
    Read/Write
    R/W
    Initial Value
    0000
    000
    0
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