PIC16C6X
DS30234D-page 132
1997 Microchip Technology Inc.
TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset
Brown-out
Reset
MCLR Reset during:
– normal operation
– SLEEP
WDT Reset
Wake-up via
interrupt or
WDT Wake-up
W
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
N/A
N/A
N/A
TMR0
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000h
0000h
PC + 1
(2)
STATUS
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0001 1xxx
000q quuu
(3)
uuuq quuu
(3)
FSR
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---x xxxx
---u uuuu
---u uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--xx xxxx
--uu uuuu
--uu uuuu
PORTB
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- -xxx
---- -uuu
---- -uuu
PCLATH
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---0 0000
---0 0000
---u uuuu
INTCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 000x
0000 000u
uuuu uuuu
(1)
PIR1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
00-- 0000
00-- 0000
uu-- uuuu
(1)
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
(1)
PIR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- ---0
---- ---0
---- ---u
(2)
TMR1L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--00 0000
--uu uuuu
--uu uuuu
TMR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
T2CON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
-000 0000
-000 0000
-uuu uuuu
SSPBUF
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
CCPR1L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--00 0000
--00 0000
--uu uuuu
RCSTA
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 -00x
0000 -00x
uuuu -uuu
TXREG
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
RCREG
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
CCPR2L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
OPTION
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
TRISA
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---1 1111
---1 1111
---u uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--11 1111
--11 1111
--uu uuuu
TRISB
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
Legend:
u
= unchanged,
x
= unknown,
-
= unimplemented bit read as '0', q = value depends on condition.
Note 1:
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h)
after execution of PC + 1.
3:
See Table 13-10 and Table 13-11 for reset value for specific conditions.