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| 型號： | PIC16C63A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Bit CMOS Microcontrollers with A/D Converter(8位、帶A/D轉(zhuǎn)換器的CMOS微控制器) |
| 中文描述： | 8位CMOS微控制器與A / D轉(zhuǎn)換器（8位，帶的A / D轉(zhuǎn)換器的的CMOS微控制器） |
| 文件頁數(shù)： | 60/184頁 |
| 文件大小： | 2230K |
| 代理商： | PIC16C63A |
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PIC16C63A/65B/73B/74B
DS30605C-page 60
2000 Microchip Technology Inc.
10.3
SSP I
2
C Operation
The SSP module in I
2
C mode fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementation of the master func-
tions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer, the RC3/SCK/SCL
pin, which is the clock (SCL), and the RC4/SDI/SDA
pin, which is the data (SDA). The user must configure
these pins as inputs or outputs through the
TRISC<4:3> bits. External pull-up resistors for the SCL
and SDA pins must be provided in the application cir-
cuit for proper operation of the I
2
C module.
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
FIGURE 10-5:
SSP BLOCK DIAGRAM
(I
2
C MODE)
The SSP module has five registers for I
2
C operation.
These are the:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - not directly accessible
SSP Address Register (SSPADD)
The SSPCON register allows control of the I
2
C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
2
C modes to be selected:
I
2
C Slave mode (7-bit address)
I
2
C Slave mode (10-bit address)
I
2
C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
I
2
C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
I
2
C START and STOP bit interrupts enabled to
support firmware Master mode, Slave is idle
Selection of any I
2
C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
Additional information on SSP I
2
C operation can be
found in the PICmicro
Mid-Range MCU Family Ref-
erence Manual (DS33023).
10.3.1
SLAVE MODE
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally generates the acknowledge (ACK) pulse, and
then loads the SSPBUF register with the received
value currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
a)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b)
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have minimum high and low
times for proper operation. The high and low times of
the I
2
C specification, as well as the requirement of the
SSP module, is shown in timing parameter #100 and
parameter #101.
Read
Write
Match Detect
SSPADD reg
START and
STOP bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/SDI/
SDA
Shift
Clock
MSb
LSb
SSPSR reg
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