參數(shù)資料
型號: PIC16C63-10/SP
廠商: Microchip Technology
文件頁數(shù): 89/126頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 PWM 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
配用: DVMCPA-ND - KIT DVR BOARD EVAL SYSTEM MXDEV1
65
AT90S/LS4433
1042H–AVR–04/03
Operation
The ADC can operate in two modes: Single Conversion and Free Run mode. In Single
Conversion mode, each conversion will have to be initiated by the user. In Free Run
mode, the ADC is constantly sampling and updating the ADC Data Register. The ADFR
bit in ADCSR selects between the two available modes.
The ADMUX Register selects which one of the six analog input channels is to be used
as input to the ADC.
The ADC is enabled by writing a logical “1” to the ADC Enable bit, ADEN in ADCSR.
The first conversion that is started after enabling the ADC will be preceded by a dummy
conversion to initialize the ADC. To the user, the only difference will be that this conver-
sion takes 12 clock cycles more than a normal conversion.
A conversion is started by writing a logical “1” to the ADC Start Conversion bit, ADSC.
This bit will stay high as long as the conversion is in progress and be set to zero by hard-
ware when the conversion is completed. If a different data channel is selected while a
conversion is in progress, the ADC will finish the current conversion before performing
the channel change.
As the ADC generates a 10-bit result, two Data Registers, ADCH and ADCL, must be
read to get the result when the conversion is complete. Special data protection logic is
used to ensure that the contents of the Data Registers belong to the same result when
they are read. This mechanism works as follows: When reading data, ADCL must be
read first. Once ADCL is read, ADC access to Data Registers is blocked. This means
that if ADCL has been read and a conversion completes before ADCH is read, none of
the registers are updated and the result from the conversion is lost. When ADCH is
read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt, ADIF, which can be triggered when a conversion com-
pletes. When ADC access to the Data Registers is prohibited between reading of ADCH
and ADCL, the interrupt will trigger even if the result gets lost.
Prescaling
Figure 45. ADC Prescaler
The ADC contains a prescaler, which divides the system clock to an acceptable ADC
clock frequency. The ADC accepts input clock frequencies in the range 50 - 200 kHz.
Applying a higher input frequency will result in a poorer accuracy (see “ADC Character-
istics” on page 71).
The ADPS0 - ADPS2 bits in ADCSR are used to generate a proper ADC clock input fre-
quency from any XTAL frequency above 100 kHz. The prescaler starts counting from
the moment the ADC is switched on by setting the ADEN bit in ADCSR. The prescaler
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
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PIC16C63-20E/SP 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT