參數(shù)資料
型號(hào): pic16c621a
廠商: Microchip Technology Inc.
英文描述: EPROM-Based 8-Bit CMOS Microcontroller(8位CMOS微控制器)
中文描述: 存儲(chǔ)器為基礎(chǔ)的8位CMOS微控制器(8位的CMOS微控制器)
文件頁(yè)數(shù): 46/112頁(yè)
文件大?。?/td> 1205K
代理商: PIC16C621A
PIC16C62X(A)
DS30235F-page 46
Preliminary
1997 Microchip Technology Inc.
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
FIGURE 9-1:
CONFIGURATION WORD
CP1
CP0
(2)
CP1
CP0
(2)
CP1
CP0
(2)
BODE
(1)
CP1
CP0
(2)
PWRTE
(1)
WDTE F0SC1
F0SC0
CONFIG
REGISTER:
Address
2007h
bit13
bit0
bit 13-8
5-4:
CP<1:0>:
Code protection bits
(2)
Code protection for 2K program memory
11
= Program memory code protection off
10
= 0400h-07FFh code protected
01
= 0200h-07FFh code protected
00
= 0000h-07FFh code protected
Code protection for 1K program memory
11
= Program memory code protection off
10
=Program memory code protection on
01
= 0200h-03FFh code protected
00
= 0000h-03FFh code protected
Code protection for 0.5K program memory
11
= Program memory code protection off
10
= Program memory code protection of
01
= Program memory code protection of
00
= 0000h-01FFh code protected
bit 7:
Unimplemented
: Read as '1'
BODEN
: Brown-out Reset Enable bit
(1)
1 = BOR enabled
0 = BOR disabled
PWRTE
: Power-up Timer Enable bit
(1)
1 = PWRT disabled
0 = PWRT enabled
bit 6:
bit 3:
bit 2:
WDTE
: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0
: Oscillator Selection bits
11
= RC oscillator
10
= HS oscillator
01
= XT oscillator
00
= LP oscillator
Note 1:
Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
2:
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