參數(shù)資料
型號(hào): PIC16C55A-04I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 78/194頁(yè)
文件大?。?/td> 0K
描述: IC MCU OTP 512X12 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 768B(512 x 12)
程序存儲(chǔ)器類型: OTP
RAM 容量: 25 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 635 (CN2011-ZH PDF)
配用: XLT28XP-ND - SOCKET TRANSITION ICE 28DIP
AC164001-ND - MODULE SKT PROMATEII 18/28DIP
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PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 167
15.2.5
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. The Break character transmit
consists of a Start bit, followed by twelve ‘0’ bits and a
Stop bit. The Frame Break character is sent whenever
the
SENDB
and
TXEN
bits
(TXSTA<3>
and
TXSTA<5>) are set while the Transmit Shift Register is
loaded with data. Note that the value of data written to
TXREG will be ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
Note that the data value written to the TXREG for the
Break character is ignored. The write simply serves the
purpose of initiating the proper sequence.
The TRMT bit indicates when the transmit operation is
active or Idle, just as it does during normal transmission.
See Figure 15-10 for the timing of the Break character
sequence.
15.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame
header made up of a Break, followed by an Auto-Baud
Sync byte. This sequence is typical of a LIN bus master.
1.
Configure the EUSART for the desired mode.
2.
Set the TXEN and SENDB bits to set up the
Break character.
3.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4.
Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5.
After the Break has been sent, the SENDB bit is
reset by hardware. The Sync character now
transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
15.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method forces configuration of the baud rate
at a frequency of 9/13 the typical speed. This allows for
the Stop bit transition to be at the correct sampling
location (13 bits for Break versus Start bit and eight
data bits for typical data).
The second method uses the auto-wake-up feature
Break Character”. By enabling this feature, the
EUSART will sample the next two transitions on RX/DT,
cause an RCIF interrupt and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Rate Detect
feature. For both methods, the user can set the ABD bit
once the TXIF interrupt is observed.
FIGURE 15-10:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TX (pin)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
SENDB
(Transmit Shift
Reg. Empty Flag)
SENDB sampled here
Auto-Cleared
Dummy Write
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