PIC18F2450/4450
DS39760A-page 174
Advance Information
2006 Microchip Technology Inc.
REGISTER 16-2:
ADCON1: A/D CONTROL REGISTER 1
U-0
R/W-0
R/W-0(1)
R/W(1)
—
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
VCFG0: Voltage Reference Configuration bit (VREF- source)
1
= VREF- (AN2)
0
= VSS
bit 4
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1
= VREF+ (AN3)
0
= VDD
bit 3-0
PCFG3:PCFG0: A/D Port Configuration Control bits:
Note 1:
The POR value of the PCFG bits depends on the value of the PBADEN
Configuration bit. When PBADEN = 1, PCFG<3:0> = 0000; when PBADEN = 0, PCFG<3:0> = 0111.
2:
AN5 through AN7 are available only on 40/44-pin devices.
A = Analog input
D = Digital I/O
PCFG3:
PCFG0
AN1
2
AN1
1
AN1
0
AN9
AN8
AN7
(2
)
AN6
(2
)
AN5
(2
)
AN4
AN3
AN2
AN1
AN0
0000(1)
A
AAAAA
A
0001
A
AAAAA
A
0010
A
AAAAA
A
0011
D
A
AAAAA
A
0100
D
A
AAAAA
A
0101
D
A
AAAAA
A
0110
D
AAAAA
A
0111(1)
D
AAAA
A
1000
DDD
D
A
1001
DDD
D
A
1010
D
DDDD
A
1011
D
DDDDD
A
1100
D
DDDDD
D
A
1101
D
DDDDD
D
A
1110
D
DDDDD
D
A
1111
D
DDDDD
D
