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| 型號： | PIC16C54C-20/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 71/194頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 512X12 18DIP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 768B（512 x 12） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 25 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | 309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE AC164001-ND - MODULE SKT PROMATEII 18/28DIP |
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PIC18F2450/4450
DS39760A-page 160
Advance Information
2006 Microchip Technology Inc.
15.1.3
AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 15-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is self-aver-
aging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. In
ABD mode, the internal Baud Rate Generator is used
as a counter to time the bit period of the incoming serial
byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detection must receive a byte with the value 55h
(ASCII “U”, which is also the LIN bus Sync character)
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and a high bit time in
order to minimize any effects caused by asymmetry of
the incoming signal. After a Start bit, the SPBRG
begins counting up, using the preselected clock source
on the first rising edge of RX. After eight bits on the RX
pin, or the fifth rising edge, an accumulated value
totalling the proper BRG period is left in the
SPBRGH:SPBRG register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status
bit (BAUDCON<7>). It is set in hardware by BRG roll-
overs and can be set or cleared by the user in software.
ABD mode remains active after rollover events and the
ABDEN bit remains set (Figure 15-2).
While calibrating the baud rate period, the BRG
registers are clocked at 1/8th the preconfigured clock
rate. Note that the BRG clock will be configured by the
BRG16 and BRGH bits. Independent of the BRG16 bit
setting, both the SPBRG and SPBRGH will be used as
a 16-bit counter. This allows the user to verify that no
carry occurred for 8-bit modes by checking for 00h in
the SPBRGH register. Refer to Table 15-4 for counter
clock rates to the BRG.
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RCIF interrupt is set
once the fifth rising edge on RX is detected. The value
in the RCREG needs to be read to clear the RCIF
interrupt. The contents of RCREG should be discarded.
TABLE 15-4:
BRG COUNTER
CLOCK RATES
15.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD
acquisition, the EUSART transmitter cannot be used
during ABD. This means that whenever the ABDEN bit
is set, TXREG cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Rate Detection will occur on
the byte
following the Break character.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator fre-
quency and EUSART baud rates are not
possible due to bit error rates. Overall
system timing and communication baud
rates must be taken into consideration
when
using
the
Auto-Baud
Rate
Detection feature.
BRG16
BRGH
BRG Counter Clock
00
FOSC/512
01
FOSC/128
10
FOSC/128
11
FOSC/32
Note:
During the ABD sequence, SPBRG and
SPBRGH are both used as a 16-bit counter,
independent of the BRG16 setting.
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| PIC16C54C-40/P | 功能描述:8位微控制器 -MCU .75KB 25 RAM 12 I/O 40MHz PDIP18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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| PIC16C54CT-04/SO | 功能描述:8位微控制器 -MCU .75KB 25 RAM 12 I/O 4MHz SOIC18 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C54CT-04/SO092 | 制造商:Microchip Technology Inc 功能描述: |
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