PIC18F2450/4450
DS39760A-page 110
Advance Information
2006 Microchip Technology Inc.
TABLE 9-9:
PORTE I/O SUMMARY
TABLE 9-10:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RE0/AN5
RE0
0
OUT
DIG
LATE<0> data output; not affected by analog input.
1
IN
ST
PORTE<0> data input; disabled when analog input enabled.
AN5
1
IN
ANA
A/D input channel 5; default configuration on POR.
RE1/AN6
RE1
0
OUT
DIG
LATE<1> data output; not affected by analog input.
1
IN
ST
PORTE<1> data input; disabled when analog input enabled.
AN6
1
IN
ANA
A/D input channel 6; default configuration on POR.
RE2/AN7
RE2
0
OUT
DIG
LATE<2> data output; not affected by analog input.
1
IN
ST
PORTE<2> data input; disabled when analog input enabled.
AN7
1
IN
ANA
A/D input channel 7; default configuration on POR.
MCLR/VPP/
RE3
— (1)
IN
ST
PORTE<3> data input; enabled when MCLRE Configuration bit
is clear.
MCLR
—
(1)
IN
ST
External Master Clear input; enabled when MCLRE Configuration bit
is set.
VPP
— (1)
IN
ANA
High-voltage detection, used for ICSP mode entry detection.
Always available regardless of pin mode.
Legend:
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input.
Note
1:
RE3 does not have a corresponding TRISE<3> bit. This pin is always an input regardless of mode.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
PORTE
—
—RE3(1,2)
RE2(3)
RE1(3)
RE0(3)
LATE(3)
—
LATE2
LATE1
LATE0
TRISE(3)
—
TRISE2
TRISE1
TRISE0
ADCON1
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0
Legend: — = unimplemented, read as ‘0’
Note 1:
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0); otherwise,
read as ‘0’.
2:
RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3:
These registers and/or bits are unimplemented on 28-pin devices.