• 參數(shù)資料
    型號: PIC16C472
    廠商: Microchip Technology Inc.
    英文描述: 14-Pin, 8-Bit CMOS OTP Microcontroller With A/D Converter(工作電壓2.5~5.5V,捕捉/比較/PWM的微控制器)
    中文描述: 14引腳,8位微控制器的CMOS檢察官辦公室的A / D轉(zhuǎn)換器(工作電壓2.5?5.5V之間,捕捉/比較/脈寬調(diào)制的微控制器)
    文件頁數(shù): 45/170頁
    文件大?。?/td> 4191K
    代理商: PIC16C472
    2003 Microchip Technology Inc.
    Preliminary
    DS40300C-page 43
    PIC16F62X
    6.0
    TIMER0 MODULE
    The Timer0 module timer/counter has the following
    features:
    8-bit timer/counter
    Readable and writable
    8-bit software programmable prescaler
    Internal or external clock select
    Interrupt on overflow from FFh to 00h
    Edge select for external clock
    Figure 6-1 is a simplified block diagram of the Timer0
    module. Additional information available in the
    PICmicro Mid-Range MCU Family Reference
    Manual, DS31010A.
    Timer mode is selected by clearing the T0CS bit
    (OPTION<5>). In Timer mode, the TMR0 will increment
    every instruction cycle (without prescaler). If Timer0 is
    written, the increment is inhibited for the following two
    cycles. The user can work around this by writing an
    adjusted value to TMR0.
    Counter mode is selected by setting the T0CS bit. In
    this mode Timer0 will increment either on every rising
    or falling edge of pin RA4/T0CKI. The incrementing
    edge is determined by the source edge (T0SE) control
    bit (OPTION<4>). Clearing the T0SE bit selects the
    rising edge. Restrictions on the external clock input are
    discussed in detail in Section 6.2.
    The prescaler is shared between the Timer0 module
    and the Watchdog Timer. The prescaler assignment is
    controlled in software by the control bit PSA
    (OPTION<3>). Clearing the PSA bit will assign the
    prescaler to Timer0. The prescaler is not readable or
    writable. When the prescaler is assigned to the Timer0
    module, prescale value of 1:2, 1:4,..., 1:256 are
    selectable. Section 6.3 details the operation of the
    prescaler.
    6.1
    TIMER0 Interrupt
    Timer0 interrupt is generated when the TMR0 register
    timer/counter overflows from FFh to 00h. This overflow
    sets the T0IF bit. The interrupt can be masked by
    clearing the T0IE bit (INTCON<5>). The T0IF bit
    (INTCON<2>) must be cleared in software by the
    Timer0 module interrupt service routine before re-
    enabling this interrupt. The Timer0 interrupt cannot
    wake the processor from SLEEP since the timer is shut
    off during SLEEP.
    6.2
    Using Timer0 with External Clock
    When an external clock input is used for Timer0, it must
    meet certain requirements. The external clock
    requirement is due to internal phase clock (T
    OSC
    )
    synchronization. Also, there is a delay in the actual
    incrementing of Timer0 after synchronization.
    6.2.1
    EXTERNAL CLOCK
    SYNCHRONIZATION
    When no prescaler is used, the external clock input is
    the same as the prescaler output. The synchronization
    of T0CKI with the internal phase clocks is
    accomplished by sampling the prescaler output on the
    Q2 and Q4 cycles of the internal phase clocks
    (Figure 6-1). Therefore, it is necessary for T0CKI to be
    high for at least 2T
    OSC
    (and a small RC delay of 20 ns)
    and low for at least 2T
    OSC
    (and a small RC delay of
    20 ns). Refer to the electrical specification of the
    desired device.
    When a prescaler is used, the external clock input is
    divided by the asynchronous ripple-counter type
    prescaler so that the prescaler output is symmetrical.
    For the external clock to meet the sampling
    requirement, the ripple-counter must be taken into
    account. Therefore, it is necessary for T0CKI to have a
    period of at least 4T
    OSC
    (and a small RC delay of 40 ns)
    divided by the prescaler value. The only requirement
    on T0CKI high and low time is that they do not violate
    the minimum pulse width requirement of 10 ns. Refer to
    parameters 40, 41 and 42 in the electrical specification
    of the desired device. See Table 17-7.
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