參數(shù)資料
型號： PIC14000T-04/SS
廠商： Microchip Technology
文件頁數(shù)： 101/153頁
文件大小： 0K
描述： IC MCU OTP 4KX14 A/D 28SSOP
產(chǎn)品培訓模塊： Asynchronous Stimulus
標準包裝： 2,100
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲器容量： 7KB（4K x 14）
程序存儲器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
包裝： 帶卷 (TR)
配用： 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 51
PIC14000
7.5.1.3
TRANSMISSION
When the R/W bit of the address byte is set and an
address match occurs, the R/W bit of the I2CSTAT
register is set. The received address is loaded into the
I2CBUF The ACK pulse will be sent on the ninth bit, and
the SCL pin is held low. The transmit data must be
loaded into the I2CBUF register, which also loads the
I2CSR register. Then the SCL pin should be enabled by
setting the CKP bit (I2CCON<4>). The eight data bits
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 7-15).
A I2CIF interrupt is generated for each data transfer
byte. The I2CIF bit must be cleared in software, and the
I2CSTAT register is used to determine the status of the
byte. The I2CIF bit is set on the falling edge of the ninth
clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. The slave
then monitors for another occurrence of the START bit.
If the SDA line was low (ACK), the transmit data must
be loaded into the I2CBUF register, which also loads
the I2CSR register. Then the SCL pin should be
enabled by setting the CKP bit (I2CCON<4>).
FIGURE 7-15: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
SCL
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
CKP (I2CCON<4>)
A7
A6
A5
A4
A3
A2
A1
ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Transmitting Data
R/W = 1
Receiving Address
1
2
3
4
56789
123
4
5
67
8
9
P
cleared in software
I2CBUF is written in software
From I2CIF interrupt
service routine
Set bit after writing to I2CBUF
S
Data in
sampled
SCL held low
while CPU
responds to I2CIF
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