參數(shù)資料
型號: PIC12LF1840T-I/MF
廠商: Microchip Technology
文件頁數(shù): 86/122頁
文件大小: 0K
描述: MCU 7KB FLASH 256B RAM XLP 8DFN
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 帶卷 (TR)
PIC12(L)F1840
DS41441B-page 66
Preliminary
2011 Microchip Technology Inc.
REGISTER 6-1:
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
R/W-1/1
R/W-0/0
CLKREN
CLKROE
CLKRSLR
CLKRDC1
CLKRDC0
CLKRDIV2
CLKRDIV1
CLKRDIV0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
CLKREN:
Reference Clock Module Enable bit
1
= Reference clock module is enabled
0
= Reference clock module is disabled
bit 6
CLKROE:
Reference Clock Output Enable bit(3)
1
= Reference clock output is enabled on CLKR pin
0
= Reference clock output disabled on CLKR pin
bit 5
CLKRSLR:
Reference Clock Slew Rate Control Limiting Enable bit
1
= Slew rate limiting is enabled
0
= Slew rate limiting is disabled
bit 4-3
CLKRDC<1:0>:
Reference Clock Duty Cycle bits
11
= Clock outputs duty cycle of 75%
10
= Clock outputs duty cycle of 50%
01
= Clock outputs duty cycle of 25%
00
= Clock outputs duty cycle of 0%
bit 2-0
CLKRDIV<2:0>
Reference Clock Divider bits
111
= Base clock value divided by 128
110
= Base clock value divided by 64
101
= Base clock value divided by 32
100
= Base clock value divided by 16
011
= Base clock value divided by 8
010
= Base clock value divided by 4
001
= Base clock value divided by 2(1)
000
= Base clock value(2)
Note 1:
In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2:
In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3:
To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration
Word 1 = 0 will result in FOSC/4. See Section 6.3 “Conflicts with the CLKR pin” for details.
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