參數(shù)資料
型號(hào): PIC12LC509AT-04I/MF
廠商: Microchip Technology
文件頁數(shù): 52/113頁
文件大小: 0K
描述: IC MCU OTP 1KX12 LV 8-DFN
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® 12C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 1.5KB(1K x 12)
程序存儲(chǔ)器類型: OTP
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 帶卷 (TR)
其它名稱: PIC12LC509AT04IMF
1999 Microchip Technology Inc.
DS40139E-page 43
PIC12C5XX
8.6.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-to-
part process variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
FIGURE 8-12: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, — = unimplemented, read as ’0’, u = unchanged
1
0
1
0
From Timer0 Clock Source
To Timer0 (Figure 8-4)
Postscaler
WDT Enable
Configuration Bit
PSA
WDT
Time-out
PS2:PS0
PSA
MUX
8 - to - 1 MUX
Postscaler
M
U
X
Watchdog
Timer
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
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