參數(shù)資料
型號: PIC12F683T-I/SN
廠商: Microchip Technology
文件頁數(shù): 162/176頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 8-SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應(yīng)用說明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標準包裝: 3,300
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
產(chǎn)品目錄頁面: 645 (CN2011-ZH PDF)
配用: AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名稱: PIC12F683T-I/SN-ND
PIC12F683T-I/SNTR
PIC12F683
DS41211D-page 84
2007 Microchip Technology Inc.
REGISTER 12-1:
CONFIG: CONFIGURATION WORD REGISTER
FCMEN
IESO
BOREN1
BOREN0
bit 15
bit 8
CPD
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
P = Programmable’
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘1’
bit 11
FCMEN: Fail-Safe Clock Monitor Enabled bit
1
= Fail-Safe Clock Monitor is enabled
0
= Fail-Safe Clock Monitor is disabled
bit 10
IESO: Internal External Switchover bit
1
= Internal External Switchover mode is enabled
0
= Internal External Switchover mode is disabled
bit 9-8
BOREN<1:0>: Brown-out Reset Selection bits(1)
11
= BOR enabled
10
= BOR enabled during operation and disabled in Sleep
01
= BOR controlled by SBOREN bit of the PCON register
00
= BOR disabled
bit 7
CPD: Data Code Protection bit(2)
1
= Data memory code protection is disabled
0
= Data memory code protection is enabled
bit 6
CP: Code Protection bit(3)
1
= Program memory code protection is disabled
0
= Program memory code protection is enabled
bit 5
MCLRE: GP3/MCLR pin function select bit(4)
1
= GP3/MCLR pin function is MCLR
0
= GP3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4
PWRTE: Power-up Timer Enable bit
1
= PWRT disabled
0
= PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled and can be enabled by SWDTEN bit of the WDTCON register
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111
= RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110
= RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101
= INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
100
= INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
011
= EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010
= HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001
= XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000
= LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note
1:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
2:
The entire data EEPROM will be erased when the code protection is turned off.
3:
The entire program memory will be erased when the code protection is turned off.
4:
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
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