參數(shù)資料
型號(hào): PIC12F683T-E/MF
廠商: Microchip Technology
文件頁數(shù): 13/176頁
文件大?。?/td> 0K
描述: IC MCU FLASH 2KX14 8DFN
Digi-Key 應(yīng)用說明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 帶卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
2007 Microchip Technology Inc.
DS41211D-page 9
PIC12F683
TABLE 3-1:
PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90
01h
TMR0
Timer0 Module Register
xxxx xxxx
02h
PCL
Program Counter’s (PC) Least Significant Byte
0000 0000
03h
STATUS
IRP(1)
RP1(1)
RP0
TO
PD
ZDC
C
0001 1xxx
04h
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
05h
GPIO
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
06h
Unimplemented
07h
Unimplemented
08h
Unimplemented
09h
Unimplemented
0Ah
PCLATH
Write Buffer for upper 5 bits of Program Counter
---0 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0Ch
PIR1
EEIF
ADIF
CCP1IF
CMIF
OSFIF
TMR2IF
TMR1IF
000- 0000
0Dh
Unimplemented
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
10h
T1CON
T1GINV
TMR1GE
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON 0000 0000 47, 90
11h
TMR2
Timer2 Module Register
0000 0000
12h
T2CON
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON
T2CKPS1
T2CKPS0 -000 0000 50, 90
13h
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
xxxx xxxx
14h
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx
15h
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0 --00 0000 75, 90
16h
Unimplemented
17h
Unimplemented
18h
WDTCON
WDTPS3
WDTPS2
WDTPS1
WDTPS0
SWDTEN ---0 1000 97, 90
19h
CMCON0
—COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
1Ah
CMCON1
T1GSS
CMSYNC ---- --10 57, 90
1Bh
Unimplemented
1Ch
Unimplemented
1Dh
Unimplemented
1Eh
ADRESH
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
xxxx xxxx
1Fh
ADCON0
ADFM
VCFG
CHS1
CHS0
GO/DONE
ADON
00-- 0000
Legend:
– = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note
1:
IRP and RP1 bits are reserved, always maintain these bits clear.
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