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參數(shù)資料
| 型號： | PIC12F675T-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 33/35頁 |
| 文件大小： | 0K |
| 描述： | IC MCU CMOS 1K FLASH W/AD 8-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
| 其它名稱： | PIC12F675-I/MFTR PIC12F675T-I/MFTR PIC12F675T-I/MFTR-ND |
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7
0787E–MICRO–3/06
AT89S53
SPI Registers Control and status bits for the Serial Periph-
eral Interface are contained in registers SPCR (shown in
are contained in the SPDR register. Writing the SPI data
register during serial data transfer sets the Write Collision
bit, WCOL, in the SPSR register. The SPDR is double buff-
ered for writing and the values in SPDR are not changed by
Reset.
Interrupt Registers The global interrupt enable bit and the
individual interrupt enable bits are in the IE register. In
addition, the individual interrupt enable bit for the SPI is in
the SPCR register. Two priorities can be set for each of the
six interrupt sources in the IP register.
Dual Data Pointer Registers To facilitate accessing exter-
nal data memory, two banks of 16-bit Data Pointer
Registers are provided: DP0 at SFR address locations
82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON
selects DP0 and DPS = 1 selects DP1. The user should
always initalize the DPS bit to the appropriate value before
accessing the respective Data Pointer register.
Power Off Flag The Power Off Flag (POF) is located at
bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during
power up. It can be set and reset under software control
and is not affected by RESET.
Table 3. WCON—Watchdog Control Register
WCON Address = 96H
Reset Value = 0000 0010B
PS2
PS1
PS0
reserved
DPS
WDTRST
WDTEN
Bit
7
6
5
4
3
2
1
0
Symbol
Function
PS2
PS1
PS0
Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16
ms. When all three bits are set to “1”, the nominal period is 2048 ms.
DPS
Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the
second bank, DP1
WDTRST
Watchdog Timer Reset. Each time this bit is set to “1” by user software, a pulse is generated to reset the watchdog
timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only.
WDTEN
Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
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