參數(shù)資料
型號(hào)： PIC12F635T-I/MD
廠商： Microchip Technology
文件頁數(shù)： 29/74頁
文件大小： 0K
描述： IC PIC MCU FLASH 1KX14 8DFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 3,300
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 帶卷 (TR)
配用： AC164326-ND - MODULA SKT PM3 20QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
Micrel, Inc.
KSZ8841-PMQL
October 2007
35
M9999-100407-1.5
Power-Management Control and Status Register (CPMC Offset 54H)
The CMPC register is a power-management control and status register. This register can control and sate power
management events. The following table shows the CMPC register bit fields.
Bit
Default
Description
31 - 16
0x0000
Reserved
15
0
PME_Status
This bit indicates that the KSZ8841-PMQL has detected a power-
management event. If bit PME_Enable is set, the KSZ8841-PMQL also
asserts the PME_N pin. This bit is cleared on power-up reset or by write
1. It is not modified by either hardware or software reset. When this bit is
cleared, the KSZ8841-PMQL deserts the PME_N pin.
14 - 9
0x00
Reserved
8
0
PME_Enable
If this bit is set, the KSZ8841-PMQL can assert the PME_N pin.
Otherwise, assertion of the PME_N pin is disabled. This bit is cleared on
power-up reset only and is not modified by either hardware or software
reset.
7 - 4
0x0
Reserved
3
0
No Soft Reset
If this bit is set (“1”), the KSZ8841-PMQL does not perform an internal
reset when transitioning from D3_hot to D0 because of PowerState
commands. Configuration context is preserved. Upon transition from
D3_hot to the D0 Initialized state, no additional operating system
intervention is required to preserve configuration context beyond writing
the PowerState bits.
If this bit is cleared (“0”), the KSZ8841-PMQL does perform an internal
reset when transitioning from D3_hot to D0 via software control of the
PowerState bits. Configuration context is lost when performing the soft
reset. Upon transition from D3_hot to the D0 state, full reinitialization
sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by a
system or bus segment reset will return to the device state D0
Uninitialized with only PME context preserved if PME is supported and
enabled.
2
0
Reserved
1 - 0
00
Power State
This field is used to set the current power state of the KSZ8841-PMQL
and to determine its power state. The definitions of the field values are:
0: D0
1: D1
2: D2
3: D3(hot)
This field gets a value of 0 after power up.
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