參數(shù)資料
型號(hào): PIC12F635-I/P
廠商: Microchip Technology
文件頁數(shù): 70/74頁
文件大?。?/td> 0K
描述: IC MCU FLASH 1KX14 8DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 60
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: DM163029-ND - BOARD PICDEM FOR MECHATRONICS
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
ACICE0201-ND - MPLABICE 8P 300 MIL ADAPTER
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
Micrel, Inc.
KSZ8841-PMQL
October 2007
72
M9999-100407-1.5
Acronyms and Glossary
BPDU
Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
CMOS
Complementary Metal
Oxide Semiconductor
A common semiconductor manufacturing technique in which positive and
negative types of transistors are combined to form a current gate that in
turn forms an effective means of controlling electrical current through a
chip.
CRC
Cyclic Redundancy Check
A common technique for detecting
data transmission errors. CRC for
Ethernet is 32 bits long.
Cut-Through
Switch
A switch typically processes received packets by reading in the full packet
(storing), then processing the packet to determine where it needs to go,
then forwarding it. A cut-through switch simply reads in the first bit of an
incoming packet and forwards the packet. Cut-through switches do not
store the packet.
DA
Destination Address
The address to send packets.
DMA
Direct Memory Access
A design in which memory on a chip is controlled independently of the
CPU.
EEPROM
Electronically Erasable
Programmable Read-
only Memory
A design in which memory on a chip can be erased by exposing it to an
electrical charge.
EISA
Extended Industry Standard
Architecture
A
bus architecture designed for PCs using 80x86 processors, or an Intel
80386, 80486 or Pentium microprocessor. EISA buses are 32
bits wide
and
support multiprocessing.
EMI
Electro-Magnetic
Interference
A naturally occurring phenomena when the electromagnetic field of one
device disrupts, impedes or degrades the electromagnetic field of another
device by coming into proximity with it. In computer technology, computer
devices are susceptible to EMI because electromagnetic fields are a
byproduct of passing electricity through a wire. Data lines that have not
been properly shielded are susceptible to data corruption by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IGMP
Internet Group
Management Protocol
The protocol defined by RFC 1112 for IP multicast transmissions.
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the network
standard for protocol reasons. In Ethernet, the medium has to be "silent"
(i.e., no data transfer) for a short period of time before a node can
consider the network idle and start to transmit. IPG is used to correct
timing differences between a transmitter and receiver. During the IPG, no
data is transferred, and information in the gap can be discarded or
additions inserted without impact on data integrity.
ISI
Inter-Symbol Interference
T
he disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA
Industry Standard
Architecture
A bus architecture used in the IBM PC/XT and
PC/AT.
Jumbo
Packet
A packet larger than the standard Ethernet packet (1500 bytes). Large
packet sizes allow for more efficient use of bandwidth, lower overhead,
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