參數(shù)資料
型號： PIC12F635-I/MD
廠商： Microchip Technology
文件頁數(shù)： 25/74頁
文件大小： 0K
描述： IC PIC MCU FLASH 1KX14 8DFN
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 91
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁面： 637 (CN2011-ZH PDF)
配用： AC164326-ND - MODULA SKT PM3 20QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
Micrel, Inc.
KSZ8841-PMQL
October 2007
31
M9999-100407-1.5
Configuration Revision Register (CFRV Offset 08H)
The CFRV register contains the KSZ8841-PMQL revision number. The following table shows the CFRV register bit
fields.
Bit
Default
Description
31 - 24
0x02
Base Class
Indicates the network controller, and is equal to 0x2.
23 - 16
0x00
Subclass
Indicates the Fast/Gigabit Ethernet chip, and is equal to 0x00.
15 - 8
0x00
Reserved
7 - 4
0x1
Revision Number
Indicates the KSZ8841-PMQL revision number, and is equal to 0x1. This
number is incremented for subsequent revision.
3 - 0
0x0
Step Number
Indicates the KSZ8841-PMQL step number, and is equal to 0x0 (chip
revision A). This number is incremented for subsequent KSZ8841-PMQL
steps within the current revision.
Configuration Latency Timer Register (CFLT Offset 0CH)
This register configures the cache line size field and the latency timer.
The following table shows the CFLT register bit fields.
Bit
Default
Description
31 - 16
0x00
Reserved
15 - 8
0x00
Configuration Latency Timer
Specifies, in units of PCI bus clocks, the value of the latency timer of the
KSZ8841-PMQL. When the KSZ8841-PMQL asserts FRAME_N, it enables
its latency timer to count. If the KSZ8841-PMQL deserts FRAME_N prior to
count expiration, the content of the latency timer is ignored. Otherwise,
after the count expires, the KSZ8841-PMQL initiates transaction
termination as soon as its GNT_N is deserted.
7 - 0
0x00
Cache Line Size
Specifies, in unit of 32-bit words(Dword), the system cache line size.
Configuration Base Memory Address Register (CBMA Offset 10H)
The CBMA register specifies the base memory address for accessing the KSZ8841-PMQL CSRs. This register must be
initialized prior to accessing any CSR with memory access.
The following table shows the CBMA register bit fields.
Bit
Default
Description
31 - 11
0
Configuration Base Memory Address
Defines the base address assigned for mapping the KSZ8841-PMQL
CSRs.
10 - 1
0
This field value is 0 when read.
0
Memory Space Indicator
Determines that the register maps into the Memory space.
The value in this field is 0.
This is a read-only field.
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參數(shù)描述
PIC12F635-IS 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
PIC12F635TE/MF 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
PIC12F635TE/MFQTP 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
PIC12F635TE/P 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
PIC12F635TE/PQTP 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8/14-PIN FLASH-BASED, 8-BIT CMOS MICROCONTROLLERS WITH NANOWATT TECHNOLOGY
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