PIC12F519
DS41319B-page 38
2008 Microchip Technology Inc.
REGISTER 8-1:
CONFIG: CONFIGURATION WORD REGISTER(1)
—CPDF
IOSCFS
MCLRE
CP
WDTE
FOSC1
FOSC0
bit 7
bit 0
bit 7
Unimplemented
: Read as ‘1’
bit 6
CPDF:
Code Protection bit - Flash Data Memory
1
= Code protection off
0
= Code protection on
bit 5
IOSCFS:
Internal Oscillator Frequency Select bit
1
= 8 MHz INTOSC frequency
0
= 4 MHz INTOSC frequency
bit 4
MCLRE:
Master Clear Enable bit
1
= GP3/MCLR pin functions as MCLR
0
= GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3
CP:
Code Protection bit - User Program Memory
1
= Code protection off
0
= Code protection on
bit 2
WDTE:
Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled
bit 1-0
FOSC<1:0>:
Oscillator Selection bits
00
= LP oscillator with 18 ms DRT(2)
01
= XT oscillator with 18 ms DRT(2)
10
= INTOSC with 1 ms DRT(2)
11
= EXTRC with 1 ms DRT(2)
Note 1:
Refer to the “PIC12F519 Memory Programming Specification”, DS41316 to determine how to
program/erase the Configuration Word.
2:
DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application
designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in
acceptable operation. Refer to Figure 11-1 and Table 11-2 for VDD rise time and stability requirements for this mode of operation.