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參數(shù)資料
| 型號： | PIC12F509-I/MS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 37/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 1KX12 8MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 637 (CN2011-ZH PDF) |
| 配用： | AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN AC164325-ND - MODULE SKT FOR 8MSOP DVA12XP080-ND - ADAPTER DEVICE FOR MPLAB-ICE |
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42
6062LS–ATARM–23-Mar-09
AT91SAM9261
6062DS
Corrected MIPS and speed on page 1.
2292
Added information on EBI NCS0 hwhen BMS = 0 in Table 8-3, “Internal Memory Mapping,” on page 18.
6062ES
2946
Updated information on JTAGSEL in Section 3-1 “Signal Description by Peripheral” on page 5 and in
2475
Reformatted Section 8. “Memories” on page 16. Inserted new Figure 8-1, “AT91SAM9261 Memory
Mapping,” on page 16 to show full product memory mapping.
2474
Removed information on Timer Counter clock assignments in Section 10.11 “Timer Counter” on page
2480
Inserted new Section 8.1.2 “Boot Strategies” on page 20 to replace Boot ROM section.
6062FS
3068
Changed pin name for ball D9 to SHDN in Table 4-1, “AT91SAM9261 Pinout for 217-ball LFBGA
3147
Updated information on shutdown pin in Section 6.5 “Shutdown Logic Pins” on page 12.
3067
Updated peripheral mnemonics in Figure 8-1, “AT91SAM9261 Memory Mapping,” on page 16.
3503
Added note to Table 10-1, “Peripheral Identifiers,” on page 28.
6062GS
3660, 3695
Updated VDDOSC, VDDPLL and VDDIOM ranges in”Features”, Table 3-1, “Signal Description by
3660
6062HS
3491
6062IS
5042
PCO - PC7 and PC12-PC13 power supplies are VDDIOP not VDDIOM.
PA30-PA31 power supplies are VDDIOP not VDDIOM
5027
rfo
Section 8.1.2 “Boot Strategies”, removed sentence pertaining to “remap”
Section 8.1.2.1 “BMS = 1, Boot on Embedded ROM”, added NANDFlash Boot.
4965
Section 5.1 “Power Supplies”, startup voltage slope requirements for VDDCORE and VDDBU added.
4844
Table 10-3, “Multiplexing on PIO Controller B,” on page 32, Note added to “PB3” comments
4835
Figure 9-3, “Power Management Controller Block Diagram,” on page 25, in the master memory
controller representation, the divider has been updated.
4241
PCO - PC7, PC8 - PC11, PC12 - PC15 power supplies are VDDIOP not VDDIOM.
6062JS
5250
Section 5.2 “Power Consumption”, startup voltage slope requirements for VDDCORE and VDDBU
removed.
5248
In Features, on page 2: Required Power Supply updated, 3.0V to 3.6V for VDDOSC and for VDDPLL
Table 13-1.
Revision History (Continued)
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Comments
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