參數(shù)資料
型號(hào)： PIC12F1840-I/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 85/122頁(yè)
文件大?。?/td> 0K
描述： MCU 7KB FLASH 256B RAM 8-PDIP
產(chǎn)品培訓(xùn)模塊： 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 60
系列： PIC® XLP™ 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 32MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-DIP（0.300"，7.62mm）
包裝： 管件
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2011 Microchip Technology Inc.
Preliminary
DS41441B-page 65
PIC12(L)F1840
6.0
REFERENCE CLOCK MODULE
The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR) and provide a secondary internal clock source
to the modulator module. This module is available in all
oscillator configurations and allows the user to select a
greater range of clock submultiples to drive external
devices in the application. The reference clock module
includes the following features:
System clock is the source
Available in all oscillator configurations
Programmable clock divider
Output enable to a port pin
Selectable duty cycle
Slew rate control
The reference clock module is controlled by the
CLKRCON register (Register 6-1) and is enabled
when setting the CLKREN bit. To output the divided
clock signal to the CLKR port pin, the CLKROE bit
must be set. The CLKRDIV<2:0> bits enable the
selection of 8 different clock divider options. The
CLKRDC<1:0> bits can be used to modify the duty
cycle of the output clock(1). The CLKRSLR bit controls
slew rate limiting.
For information on using the reference clock output
with the modulator module, see Section 23.0 “Data
6.1
Slew rate
The slew rate limitation on the output port pin can be
disabled. The Slew Rate limitation can be removed by
clearing the CLKRSLR bit in the CLKRCON register.
6.2
Effects of a Reset
Upon any device Reset, the reference clock module is
disabled. The user’s firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.
6.3
Conflicts with the CLKR pin
There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:
LP, XT or HS oscillator mode is selected.
CLKOUT function is enabled.
Even if either of these cases are true, the module can
still be enabled and the reference clock signal may be
used in conjunction with the modulator module.
6.3.1
OSCILLATOR MODES
If LP, XT or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
for more informa-
tion on different oscillator modes.
6.3.2
CLKOUT FUNCTION
The CLKOUT function has a higher priority than the
reference clock module. Therefore, if the CLKOUT
function is enabled by the CLKOUTEN bit in Configura-
tion Word 1, FOSC/4 will always be output on the port
for more information.
6.4
Operation During Sleep
As the reference clock module relies on the system
clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.
Note 1:
If the base clock rate is selected without
a divider, the output clock will always
have a duty cycle equal to that of the
source clock, unless a 0% duty cycle is
selected. If the clock divider is set to base
clock/2, then 25% and 75% duty cycle
accuracy will be dependent upon the
source clock.
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