參數(shù)資料
型號(hào)： PIC12C672-04I/SM
廠商： Microchip Technology
文件頁數(shù)： 102/129頁
文件大?。?/td> 0K
描述： IC MCU OTP 2KX14 A/D 8-SOIJ
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 90
系列： PIC® 12C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 3.5KB（2K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 管件
配用： XLT08SO-1-ND - SOCKET TRANSITION 8SOIC 150/208
AC164312-ND - MODULE SKT FOR PM3 16SOIC
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1048-ND - ADAPTER 8-SOIC TO 8-DIP
309-1047-ND - ADAPTER 8-SOIC TO 8-DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
PIC12C67X
DS30561B-page 74
1999 Microchip Technology Inc.
BTFSS
Bit Test f, Skip if Set
Syntax:
[
label ] BTFSS f,b
Operands:
0
≤ f ≤ 127
0
≤ b < 7
Operation:
skip if (f<b>) = 1
Status Affected:
None
Encoding:
01
11bb
bfff
ffff
Description:
If bit ’b’ in register ’f’ is ’1’, then the
next instruction is skipped.
If bit ’b’ is ’1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOP is executed instead,
making this a 2 cycle instruction.
Words:
1
Cycles:
1(2)
Example
HERE
FALSE
TRUE
BTFSS
GOTO
FLAG,1
PROCESS_CO
DE
Before Instruction
PC =
address
HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CALL
Call Subroutine
Syntax:
[
label ] CALL k
Operands:
0
≤ k ≤ 2047
Operation:
(PC)+ 1
→ TOS,
k
→ PC<10:0>,
(PCLATH<4:3>)
→ PC<12:11>
Status Affected:
None
Encoding:
10
0kkk
kkkk
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two cycle instruction.
Words:
1
Cycles:
2
Example
HERE
CALL
THER
E
Before Instruction
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1
CLRF
Clear f
Syntax:
[
label ] CLRF
f
Operands:
0
≤ f ≤ 127
Operation:
00h
→ (f)
1
→ Z
Status Affected:
Z
Encoding:
00
0001
1fff
ffff
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
Words:
1
Cycles:
1
Example
CLRF
FLAG_REG
Before Instruction
FLAG_REG
=
0x5A
After Instruction
FLAG_REG
=
0x00
Z=
1
CLRW
Clear W
Syntax:
[
label ] CLRW
Operands:
None
Operation:
00h
→ (W)
1
→ Z
Status Affected:
Z
Encoding:
00
0001
0000
0011
Description:
W register is cleared. Zero bit (Z)
is set.
Words:
1
Cycles:
1
Example
CLRW
Before Instruction
W
=
0x5A
After Instruction
W
=
0x00
Z=
1
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