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參數(shù)資料
| 型號： | PIC12C509-04E/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 51/113頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 1KX12 8DIP |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus |
| 標準包裝： | 60 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.5KB（1K x 12） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 41 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 配用： | DVMCPA-ND - KIT DVR BOARD EVAL SYSTEM MXDEV1 DVA12XP080-ND - ADAPTER DEVICE FOR MPLAB-ICE |
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PIC12C5XX
DS40139E-page 42
1999 Microchip Technology Inc.
FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
VDD
MCLR
INTERNAL POR
DRT TIME-OUT
INTERNAL RESET
TDRT
V1
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1
≥ VDD min.
8.5
Device Reset Timer (DRT)
In the PIC12C5XX, DRT runs from RESET and varies
based on oscillator selection (see Table 8-5.)
The DRT operates on an internal RC oscillator. The
processor is kept in RESET as long as the DRT is
active. The DRT delay allows VDD to rise above VDD
min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (VIHMCLR)
level. Thus, programming GP3/MCLR/VPP as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the GP3/
MCLR/VPP pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog
Timer time-out. This is particularly important for
applications using the WDT to wake from SLEEP
mode automatically.
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the GP5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
The
WDT
can
be
permanently
disabled
by
programming the configuration bit WDTE as a ’0’
(Section 8.1). Refer to the PIC12C5XX Programming
Specifications to determine how to access the
configuration word.
TABLE 8-5:
DRT (DEVICE RESET TIMER
PERIOD)
Oscillator
Configuration
POR Reset
Subsequent
Resets
IntRC &
ExtRC
18 ms (typical)
300 s (typical)
XT & LP
18 ms (typical)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC12C509-04I/JW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PIC12C509-04I/P | 功能描述:8位微控制器 -MCU 1.5KB 41 RAM 6 I/O 4MHz Ind Temp PDIP8 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC12C509-04I/SM | 功能描述:8位微控制器 -MCU 1.5KB 41 RAM 6 I/O 4MHz Ind Temp SOIC8 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC12C509-04I/SN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| PIC12C509A | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin, 8-Bit CMOS Microcontrollers |
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