參數(shù)資料
型號(hào): PIC10F202T-E/OT
廠商: Microchip Technology
文件頁(yè)數(shù): 17/94頁(yè)
文件大小: 0K
描述: IC PIC MCU FLASH 512X12 SOT23-6
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 3,000
系列: PIC® 10F
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 3
程序存儲(chǔ)器容量: 768B(512 x 12)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 24 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: SOT-23-6
包裝: 帶卷 (TR)
配用: AC162059-ND - HEADER INTRFC MPLAB ICD2 8/14PIN
XLT06SOT-ND - SOCKET TRAN ICE 6SOT W/CABLE
AC163020-ND - ADAPTER PROGRAMMER PIC10F2XX
AC164321-ND - MODULE SKT 6L PM3 SOT23
PIC10F200/202/204/206
DS41239D-page 22
2007 Microchip Technology Inc.
4.7
Program Counter
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The Program Counter
Low (PCL) is mapped to PC<7:0>.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are pro-
vided by the instruction word. However, PC<8> does
not come from the instruction word, but is always
cleared (Figure 4-5).
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PC, ADDWF PC and
BSF PC,5.
FIGURE 4-5:
LOADING OF PC
BRANCH INSTRUCTIONS
4.7.1
EFFECTS OF RESET
The PC is set upon a Reset, which means that the PC
addresses the last location in program memory (i.e.,
the oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 0000h and
begin executing user code.
4.8
Stack
The PIC10F200/204 devices have a 2-deep, 8-bit wide
hardware PUSH/POP stack.
The PIC10F202/206 devices have a 2-deep, 9-bit wide
hardware PUSH/POP stack.
A CALL instruction will PUSH the current value of Stack 1
into Stack 2 and then PUSH the current PC value,
incremented by one, into Stack Level 1. If more than two
sequential CALLs are executed, only the most recent two
return addresses are stored.
A RETLW instruction will POP the contents of Stack
Level 1 into the PC and then copy Stack Level 2
contents into level 1. If more than two sequential
RETLWs are executed, the stack will be filled with the
address previously stored in Stack Level 2.
Note:
Because PC<8> is cleared in the CALL
instruction or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
PC
87
0
PCL
Instruction Word
GOTO Instruction
CALL or Modify PCL Instruction
PC
87
0
PCL
Instruction Word
Reset to ‘0’
Note 1: The W register will be loaded with the lit-
eral value specified in the instruction. This
is particularly useful for the implementa-
tion of the data look-up tables within the
program memory.
2: There are no Status bits to indicate stack
overflows or stack underflow conditions.
3: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
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