參數(shù)資料
型號: PI90LVB16L
廠商: Pericom
文件頁數(shù): 1/12頁
文件大小: 0K
描述: IC CLOCK BUFFER MUX 1:6 24-TSSOP
產(chǎn)品變化通告: Product Discontinuation Notice 29/May/2007
標(biāo)準(zhǔn)包裝: 62
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/無
輸入: BLVDS
輸出: CMOS,LVTTL
頻率 - 最大: 160MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
1
PS8536C
11/11/08
Features
Master/Slave clock selection in a backplane application
160 MHz operation (typical)
100ps duty cycle distortion (typical)
50ps channel to channel skew (typical)
3.3V power supply design
Glitch-free power on at CLKI/O pins
Low Power design (16mA @ 3.3V static)
Accepts small swing (300mV typical) differential signal levels
Industrial temperature operating range (–40°C to +85°C)
Packaging: (Pb-free & Green available)
— 24-pin TSSOP (L)
General Description
PI90LVB16isasix-channelLVTTLclockdistributiondriverwith50
picosecond channel-to-channel skew. It translates one BLVDS
(BusLow-VoltageDifferentialSignaling)inputsignalintosixLVTTL-
compatible output signals for distribution to adjacent chips on the
sameboard.ThePI90LVB16acceptsBLVDS(300mVtypical)differ-
ential input levels, and translates them to 3V CMOS output levels.
The 160MHz PI90LVB16 can be the master clock, driving inputs of
other clock I/O pins in a multipoint environment. It can also drive
the BLVDS backplane with a separate channel acting as a return/
source LVTTL clock source. The master/slave clock selection of the
driving source is controlled by the CrdCLKIN and the DE pins. An
output enable pin OE, when high, forces all CLKOUT pins high.
A backplane clock distribution network must be able to drive many
transmission line stubs. The Bus LVDS feature of the PI90LVB16 is
ideal for driving data transfers in large, high-performance backplane
system applications. The device can be used as a source synchro-
nous driver to distribute clock signals within data and telecommu-
nications systems.
FunctionDiagram
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Delay
MUX
CLKOUT0
CLKOUT1
CLKOUT5
CrdCLKIN
D
R
DE
OE
CLKI/0–
CLKI/0+
Receive Mode Truth Table
t
u
p
n
I
t
u
p
t
u
O
E
OE
DK
L
C
d
r
C
N
I
)
O
/
I
K
L
C
(
)
+
O
/
I
K
L
C
(K
L
C
T
U
O
HH
X
H
LH
X
D
I
V
V
7
0
.
0H
LH
X
D
I
V
V
7
0
.
0
–L
L = Low Logic State; H = High Logic State; X = Irrelevant
Z = High Impedance
t
u
p
n
It
u
p
t
u
O
E
OE
DK
L
C
d
r
C
N
I
+
O
/
I
K
L
C–
O
/
I
K
L
CK
L
C
T
U
O
LL
L
H
L
LL
H
L
H
HL
L
H
HL
H
L
H
HH
X
Z
H
Driver Mode Truth Table
08-0295
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