參數(shù)資料
型號(hào): PI90LVB010WE
廠商: Pericom
文件頁(yè)數(shù): 1/9頁(yè)
文件大小: 0K
描述: IC SNGL BUS LVDS TXRX 8-SOIC
標(biāo)準(zhǔn)包裝: 97
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
1
4/20/11
DE
DO-/RI-
DO+/RI+
RE
GND
DIN
VCC
ROUT
1
2
3
4
8
7
6
5
Single Bus LVDS Transceiver
Features
Bus LVDS Signaling (BLVDS)
Designed for Double Termination Applications
Balanced Output Impedance
Light Bus Loading: 5pF typical
Glitch-free power up/down (Driver Disabled)
Operates from a 3.3V supply
High Signaling Rate Capability: >100Mbps
Driver:
– ±250mV Differential Swing into a 27 load
– Propagation Delay of 1.5ns typ.
– Low Voltage TTL (LVTTL) Inputs are 5V Tolerant
Receiver:
– Accepts ±50mV (min.) Differential Swing with up to 2.0V
ground potential difference
– Propagation Delay of 3.3ns typical
– Low Voltage TTL (LVTTL) Outputs
– Open, Short, and Terminated Fail Safe
Bus terminal ESD exceeds 10kV
Industrial Temperature Operation (–40°C to +85°C)
Packaging (Pb-free & Green available):
– 8-lead SOIC (W)
– 8-lead MSOP (U)
PI90LVB010
Description
The PI90LVB010 is a differential line driver and receiver (trans-
ceiver) that is similar to the IEEE1596.3 SCI and ANSI/TIA/EIA-
644LVDS standards, the difference is that the driver output current
is higher.This modification enables true half-duplex operation with
more than one LVDS driver or with two line transmission resistors
over a 50 differential transmission line. To minimize bus loading,
the driver outputs and receiver inputs are internally connected. The
logic interface provides maximum flexibility resulting from four
separate lines that are provided: DIN, DE, RE, and ROUT.
This device also feature flow-through which allows easy PCB
routing for short stubs between the bus pins and the connector.
The driver has 10mA drive capability, allowing it to drive heavily
loaded backplanes, with impedance as low as 27.
The driver translates between TTL levels (single-ended) to Low
Voltage Differential Signaling levels. This allows for high-speed
operation, while consuming minimal power with reduced EMI. In
addition the differential signaling provides common mode noise
rejection of ±1V.
Block Diagram
Pin Configuration
DIN
ROUT
DE
RE
D0+/RI+
D0–/RI–
11-0055
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