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參數(shù)資料
| 型號： | PI90LV14Q |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 1:5 Clock Distribution |
| 中文描述： | 1:5時鐘分配 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 121K |
| 代理商： | PI90LV14Q |
1
PS8538 04/25/01
PI90LV14 Block Diagram
Features
Meets and Exceeds the Requirements of ANSI
TIA/EIA-644-1995
Designed for clocking rates up to 320MHz
Operates from a single 3.3V Supply
Low Voltage Differential Signaling (LVDS) with Output
Voltages of ±350mV into a 100
load
Choice between LVDS or TTL clock input
Synchronous Enable/Disable
Clock outputs default LOW when inputs open
Multiplexed clock input
- Internal 300k
pullup resistor on input pins
- CLK and CLK have 110
internal termination (PI90LVT14)
50ps Output-to-Output Skew
475ps typical propagation delay
Bus Pins are high impedance when disabled or with
V
CC
less than 1.5V
TTL inputs are 5V Tolerant
Power Dissipation at 400Mbits/s of 150mW
Function compatible to Motorola (PECL)
MC100EL14 and Micrel/Synergy (PECL)
SY100EL14V
>9kV ESD Protection
20-pin TSSOP (L) and QSOP (Q) packages
Description
The PI90LV14 implements low voltage differential signaling (LVDS)
to achieve clocking rates as high as 320MHz with low skew.
The PI90LV14 is a low-skew 1:5 clock distribution chip which
incorporates multiplexed clock inputs to allow for distribution of a
lower-speed, single-ended clock or a high-speed system clock.
When LOWthe SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. Because the internal flip-flop is clocked on the falling edge
of the input clock, all associated specification limits are referenced
to the negative edge of the clock input.
The intended application of these devices and signaling technique
is for high-speed clock distribution between boards.
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Pin Descriptions
K
L
C
K
L
C
S
L
E
S
*
N
E
+
T
U
O
K
L
C
L
X
L
L
L
H
X
L
L
H
X
L
H
L
L
X
H
H
L
H
↓
↓
X
H
*
Z
Function Table
* On next negative transition of CLK, or SCLK
EN
CLK
GND
SEL
GND
CLK
SCLK
GND
V
CC
V
CC
12
11
13
14
15
16
19
20
17
18
CLK5
OUT–
CLK5
OUT+
10
9
CLK4
OUT–
CLK4
OUT+
8
7
CLK3
OUT–
CLK3
OUT+
6
5
CLK2
OUT–
CLK2
OUT+
4
3
CLK1
OUT–
CLK1
OUT+
2
1
D
Q
V
1
0
110
PI90LVT14
Only
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI90LVT14 | 1:5 Clock Distribution |
| PI90LVT14L | 1:5 Clock Distribution |
| PI90LVT14Q | 1:5 Clock Distribution |
| PI90LVP10W | LVTTL to Differential LVPECL Translator with Enable |
| PI90LVP10 | LVTTL to Differential LVPECL Translator with Enable |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI90LV14QE | 功能描述:時鐘驅(qū)動器及分配 1:5 LVDS Clock Distribution RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| PI90LV14QEX | 功能描述:時鐘驅(qū)動器及分配 1:5 LVDS Clock Distribution RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| PI90LV179 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V LVDS High-Speed Differential Line Drivers and Receivers |
| PI90LV179U | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V LVDS High-Speed Differential Line Drivers and Receivers |
| PI90LV179UEX | 功能描述:總線收發(fā)器 Single LVDS Transceiver Pair RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
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