參數(shù)資料
型號(hào)： PI7C8150MA
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 86/106頁(yè)
文件大小： 904K
代理商： PI7C8150MA
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
76
August 22, 2002 – Revision 1.02
6
Delayed Read –
No Data From
Target
R/W
Controls PI7C8150’s ability to assert P_SERR_L when it is unable to
transfer any read data from the target after 2
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
7
Reserved
R/O
14.1.39
GPIO DATA AND CONTROL REGISTER – OFFSET 64h
Bit
Function
Type
Description
Writing 1 to any of these bits drives the corresponding bit LOW on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
11:8
GPIO Output
Write-1-to-Clear
R/WC
Reset to 0.
Writing 1 to any of these bits drives the corresponding bit HIGH on
the GPIO[3:0] bus if it is programmed as bidirectional. Data is
driven on the PCI clock cycle following completion of the
configuration write to this register. Bit positions corresponding to
GPIO pins that are programmed as input only are not driven. Writing
0 has no effect and will show last the last value written when read.
15:12
GPIO Output
Write-1-to-Set
R/WS
Reset to 0.
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as an input only. The output driver is tristated.
Writing 0 to this register has no effect and will reflect the last value
written when read.
19:16
GPIO Output
Enable Write-1-
to-Clear
R/WC
Reset to 0.
Writing 1 to and of these bits configures the corresponding
GPIO[3:0] pin as bidirectional. The output driver is enabled and
drives the value set in the output data register (65h). Writing 0 to this
register has no effect and will reflect the last value written when read.
23:20
GPIO Output
Enable Write-1-
to-Set
R/WS
Reset to 0.
14.1.40
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Bit
Function
Type
Description
If either bit is 0, then S_CLKOUT [0] is enabled.
If both bits are 1, then S_CLKOUT [0] is disabled.
If either bit is 0, then S_CLKOUT [1] is enabled.
If both bits are 1, then S_CLKOUT [1] is disabled.
If either bit is 0, then S_CLKOUT [2] is enabled.
If both bits are 1, then S_CLKOUT [2] is disabled.
If either bit is 0, then S_CLKOUT [3] is enabled.
If both bits are 1, then S_CLKOUT [3] is disabled.
If bit is 0, then S_CLKOUT [4] is enabled.
If bit is 1, then S_CLKOUT [4] is disabled and driven low.
If bit is 0, then S_CLKOUT [5] is enabled.
If bit is 1, then S_CLKOUT [5] is disabled and driven low.
If bit is 0, then S_CLKOUT [6] is enabled.
If bit is 1, then S_CLKOUT [6] is disabled and driven low.
1:0
Clock 0 disable
R/W
3:2
Clock 1 disable
R/W
5:4
Clock 2 disable
R/W
7:6
Clock 3 disable
R/W
8
Clock 4 disable
R/W
9
Clock 5 disable
R/W
10
Clock 6 disable
R/W
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參數(shù)描述
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