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參數(shù)資料
| 型號： | PI74SSTVF16857AEX |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC REGIST BUFF 14BIT DDR 48TSSOP |
| 標準包裝： | 1,500 |
| 系列： | 74SSTVF |
| 邏輯類型： | DDR 的寄存緩沖器 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 位數(shù)： | 14 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
1
PS8656A
05/27/03
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
ProductDescription
Pericom Semiconductor’s PI74SSTVF16857 series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857 universal bus driver is designed
for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTVF16857 is characterized for operation from
0° to 70°C.
Product Features
PI74 SSTVF16857 is designed for low-voltage operation,
2.5VforPC1600~PC2700;2.6VforPC3200
Supports SSTL_2 Class I output specifications
SSTL_2 Input and Output Levels
Designed for DDR Memory
Flow-Through Architecture
Packaging Options (Pb-free available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
ProductPinConfiguration
ProductPinDescription
48-Pin
A,K
s
t
u
p
n
Is
t
u
p
t
u
O
T
E
S
E
RK
L
CK
L
CD
Q
LX
X
L
H
↑↓
HH
Η↑
↓
LL
HH
r
o
LH
r
o
LX
o
Q
)
2
(
TruthTable(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = TransitionLOW-to-HIGH
↓ =TransitionHIGH-to-LOW
X = Irrelevant
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74SSTVF16857
14-Bit Registered Buffer
2. Output level before the
indicated steady state
input conditions were
established.
TO 13 OTHER CHANNELS
RESET
CLK
38
39
VREF
D1
48
35
D
R
CLK
Q1
1
CLK
V
34
PinName
Description
RESET
Reset (Active Low)
CLK
Clock Input
CLK
Clock Input
D
Data Input
Q
Data Output
GND
Ground
VDD
Core Supply Voltage
VDDQ
Output Supply Voltage
VREF
Input Reference Voltage
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI74SSTVF16857AX | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI74SSTVF16857KE | 功能描述:IC REG BUFFER 14BIT 48TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:74SSTVF 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應商設備封裝:48-TSSOP 包裝:帶卷 (TR) |
| PI74SSTVF16857KX | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 14-CH CMOS 48-Pin TVSOP T/R |
| PI74SSTVF16859A | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube |
| PI74SSTVF16859AE | 功能描述:寄存器 13/26B Registered Buffer RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
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