參數(shù)資料
型號: PI74FCT16823AT
廠商: Pericom Semiconductor Corp.
英文描述: Fast CMOS 18-Bit Registers
中文描述: 快速CMOS 18位寄存器
文件頁數(shù): 7/8頁
文件大?。?/td> 80K
代理商: PI74FCT16823AT
PI74FCT16823T/162823/162H823T
18-BIT REGISTERS
7
PS2040A 03/11/96
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74FCT162823T Switching Characteristics over Operating Range
162823AT
162823BT
162823CT
162823DT
162823ET
Com.
Com.
Com.
Com.
Com.
Parameters
Description
Conditions
(1)
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
t
PLH
t
PHL
Propagation Delay
X
CLK to
X
Q
X
C
L
= 50 pF
R
L
= 500
C
L
= 300 pF
(3)
R
L
= 500
C
L
= 50 pF
R
L
= 500
C
L
= 50 pF
R
L
= 500
C
L
= 300 pF
(3)
R
L
= 500
C
L
= 5 pF
(3)
R
L
= 500
C
L
= 50 pF
R
L
= 500
C
L
= 50 pF
R
L
= 500
1.5
10.0
1.5
7.5
1.5
6.0
1.5
5.0
1.5
4.4
ns
1.5
20.0
1.5
15.0
1.5
12.5
1.5
8.5
1.5
8.0
ns
t
PHL
Propagation Delay
X
CLR to
X
Q
X
Output Enable Time
X
OE to
X
Q
X
1.5
14.0
1.5
9.0
1.5
8.0
1.5
5.0
1.5
4.4
ns
t
PZH
t
PZL
1.5
12.0
1.5
8.0
1.5
7.0
1.5
4.8
1.5
4.4
ns
1.5
23.0
1.5
15.0
1.5
12.5
1.5
10.0
1.5
9.0
ns
t
PHZ
t
PLZ
Output Disable Time
(3)
X
OE to
X
Q
X
1.5
7.0
1.5
6.5
1.5
6.2
1.5
5.0
1.5
4.0
ns
1.5
8.0
1.5
7.5
1.5
6.5
1.5
5.0
1.5
4.0
ns
t
SU
Setup Time HIGH or
LOW,
X
D
X
to
X
CLK
Hold Time HIGH or
LOW,
X
D
X
to
X
CLK
Setup Time HIGH or
LOW,
X
CLKEN to
X
CLK
Hold Time HIGH or
LOW,
X
CLKEN to
X
CLK
xCLK Pulse Width
HIGH or LOW
(3)
xCLR Pulse Width LOW
(3)
Recovery Time
(3)
X
CLR to
X
CLK
Output Skew
(4)
4.0
3.0
3.0
3.0
1.5
ns
t
H
2.0
1.5
1.5
1.5
0
ns
t
SU
4.0
3.0
3.0
3.0
2.5
ns
t
H
2.0
0
0
0
0
ns
t
W
7.0
6.0
6.0
6.0
3.0
ns
t
W
t
REM
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
3.0
3.0
ns
ns
t
SK
(
O
)
0.5
0.5
0.5
0.5
0.5
ns
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not production tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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