參數(shù)資料
型號(hào): PI74AVC16834A
廠商: Pericom
文件頁(yè)數(shù): 9/10頁(yè)
文件大?。?/td> 0K
描述: IC UNIV BUS DVR 18BIT 56TSSOP
產(chǎn)品變化通告: Product Discontinuation Notice 11/Feb/2008
標(biāo)準(zhǔn)包裝: 35
系列: 74AVC
邏輯類型: 通用總線驅(qū)動(dòng)器
電路數(shù): 18 位
輸出電流高,低: 12mA,12mA
電源電壓: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 管件
8
PS8376G 10/27/09
PI74AVC16834
18-Bit Universal Bus Driver
with 3-State Outputs
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Parameter Measurement Information (VCC = 2.5V ±0.2V)
Load Circuit
Voltage Waveforms
Setup and Hold Times
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Pulse Duration
Voltage Waveforms
Enable and Disable Times
Notes:
CL includes probe and jig capacitance.
Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, ZO = 50Ω, tr ≤2ns, tr ≤2ns.
The outputs are measured one at a time with one transition per measurement.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as tdis.
tPLH and tPHL are the same as tdis.
Figure 2. Load Circuit and Voltage Waveforms
CL=30pF
500
From Output
Under Test
GND
2 x VCC
Open
500
S1
Timing
Input
Data
Input
VCC
0V
VCC
VCC/2
0V
tsu
th
Input
tPLH
Output
Vcc/2
VCC
VOH
VOL
0V
Vcc/2
Input
VCC
VCC/2
0V
tW
Output
Control
(Low-level
enabling)
Output
Waveform 2
S1 at GND
tPZL
tPLZ
0V
VOL
0V
Output
Waveform 1
S1 at 2 x VSS
VOH –0.15V
VOL +0.15V
tPHZ
tPZH
VCC/2
VCC
VOH
T
S
E
T1
S
t d
p
t
/
Z
L
P
t L
Z
P
t
/
Z
H
P
t H
Z
P
n
e
p
O
V
x
2
C
D
N
G
09-0003
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