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參數(shù)資料
| 型號： | PI74ALVCH162601A |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UNIV BUS TXRX 18BIT 56TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 17/Feb/2006 |
| 標(biāo)準(zhǔn)包裝： | 35 |
| 系列： | 74ALVCH |
| 邏輯類型： | 通用總線收發(fā)器 |
| 電路數(shù)： | 18 位 |
| 輸出電流高，低： | 32mA，64mA; 12mA，12mA |
| 電源電壓： | 2.3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
1
PS8093E 05/23/06
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PI74ALVCH162601
18-Bit Universal Bus Transceiver
with 3-State Outputs
Logic Block Diagram
Product Features
Designed for low voltage operation, VCC = 2.3V to 3.6V
Hysteresis on all inputs
Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at –40°C to +85°C
Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
ProductDescription
The PI74ALVCH162601 uses D-type latches and D-type flip-flops
with 3-state outputs to allow data flow in transparent, latched, and
clocked modes.
Data flow in each direction is controlled by Output Enable (OEAB
andOEBA),LatchedEnable(LEABandLEBA),andClock(CLKAB
andCLKBA)inputs.TheclockcanbecontrolledbytheClockEnable
(CLKENABandCLKENBA)inputs. ForA-to-Bdataflow,thedevice
operates in the transparent mode when LEAB is HIGH. When LEAB
is LOW, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A-bus is stored in the latch/flip-flop on the
low-to-high transition of CLKAB. When OEAB is low, the outputs
are active. When OEAB is HIGH, the outputs are in the high-
impedance state.
DataflowforBtoAissimilartothatofAtoBbutusesOEBA,LEBA,
CLKBA,andCLKENBA.
To reduce overshoot and undershoot, the B-port outputs include
26
Ω series resistors.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
The PI74ALVCH162601 has “Bus Hold” which retains the data
input’s last state whenever the data input goes to high-impedance
preventing “floating” inputs and eliminating the need for pullup/
down resistors.
06-0134
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI74ALVCH162601V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit Bus Transceiver |
| PI74ALVCH16260A | 功能描述:IC 12/14-BIT MUX/LATCH 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 鎖銷 系列:74ALVCH 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74VCX 邏輯類型:D 型透明鎖存器 電路:8:8 輸出類型:三態(tài) 電源電壓:1.8 V ~ 3.6 V 獨立電路:2 延遲時間 - 傳輸:1.5ns 輸出電流高，低:6mA，6mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
| PI74ALVCH16260A56 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
| PI74ALVCH16260V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
| PI74ALVCH16260V56 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Bus Exchanger |
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