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參數(shù)資料
| 型號(hào)： | PI6CVF857AE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK DVR DDR-SDRAM 48TSSOP |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR，SDRAM DIMM |
| 輸入： | SSTL-2 |
| 輸出： | SSTL-2 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 220MHz |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
1
PS8683D
11/12/08
Product Description
PI6CVF857PLLclockdeviceisdevelopedforregisteredDDRDIMM
applications. The device is a zero-delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten differential pairs of
clockoutputs(Y[0:9],Y[0:9]),andonedifferentialpairfeedbackclock
outputs (FBOUT,FBOUT) . The clock outputs are controlled by the
inputclocks(CLK,CLK),thefeedbackclocks(FBIN,FBIN),the2.5V
LVCMOS input (PWRDWN), and the Analog Power input (AVDD).
When input PWRDWN is low while power is applied, the input
receiversaredisabled,thePLListurnedoff,andthedifferentialclock
outputs are 3-stated. When the AVDD is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
willenteralowpowermode.Aninputfrequencydetectioncircuitwill
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CVF857 clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).
The PI6CVF857 is also able to track Spread Spectrum Clocking for
reduced EMI.
Product Features
Operating Frequency up to 220 MHz for PC3200 Registered
DIMM applications
Distributes one differential clock input pair to ten differential
clock output pairs
Inputs(CLK,CLK)and(FBIN,FBIN)
Input PWRDWN: LVCMOS
Outputs (Yx,Yx),(FBOUT,FBOUT)
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input
Operatesat2.5VforPC1600,PC2100,PC2700,
and2.6VforPC3200
Packaging (Pb-free & Green available):
– 48-pin TSSOP
Block Diagram
PI6CVF857
1:10 PLL Clock Driver for
2.5V DDR-SDRAM Memory
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Y0
Y1
PWRDWN
AVDD
FBIN
CLK
PLL
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
FBOUT
Powerdown
and Test
Logic
08-0298
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CVF857AEX | 功能描述:鎖相環(huán) - PLL DDR Clock Buffer SSTL2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CVF857AX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 60MHz to 220MHz 48-Pin TSSOP T/R |
| PI6CVF857NF | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:1:10 PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CVF857ZDE | 功能描述:鎖相環(huán) - PLL DDR Clock Buffer SSTL2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CVF857ZDEX | 功能描述:鎖相環(huán) - PLL DDR Clock Buffer SSTL2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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