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參數(shù)資料
| 型號(hào)： | PI6CV855 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory |
| 中文描述： | PLL時(shí)鐘驅(qū)動(dòng)器2.5V的薩里衛(wèi)星技術(shù)有限公司2的DDR SDRAM內(nèi)存 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | PI6CV855 |
1
PS8545 06/20/01
Product Description
PI6CV855 PLL clock device is developed for SSTL_DDR SDRAM
applications. This PLL Clock Buffer is designed for 2.5 V
DDQ
and
2.5V AV
DD
operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
input pair (CLK, CLK) to five differential pairs of clock outputs
(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the
Analog Power input (AV
DD
). When the AV
DD
is strapped low, the
PLL is turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
will enter a low power mode. In low power mode, PLL is turned OFF,
Y[0:4] and Y[0:4] outputs are 3-stated.
The PI6CV855 is able to track Spread Spectrum Clocking to reduce
EMI.
Product Features
PLL clock distribution optimized for SSTL_2 DDR SDRAM
applications.
Distributes one differential clock input pair to five differential
clock output pairs.
Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2
Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AV
DD
= 2.5V for core circuit and internal PLL,
and V
DDQ
= 2.5V for differential output drivers
Available Package:
Plastic 28-pin TSSOP
Block Diagram
PI6CV855
PLL Clock Driver for 2.5V
SSTL 2 DDR SDRAM Memory
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Y0
Y0
Y1
AV
DD
FBIN
FBIN
CLK
CLK
PLL
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Logic
and
Test Ciruit
V
DDQ
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Y4
Y4
FBIN
FBIN
V
DDQ
GND
Y3
Y3
GND
V
DDQ
FBOUT
FBOUT
V
DDQ
GND
GND
Y0
Y0
CLK
AV
DD
Y1
V
DDQ
AGND
GND
Y2
Y2
Y1
28-Pin
L
Pin Configuration
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6CV855L | PLL Clock Driver for 2.5V SSTL 2 DDR SDRAM Memory |
| PI6CV857LA | PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CV857 | PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CV857L | PLL Clock Driver for 2.5V DDR-SDRAM Memory |
| PI6CX100-27 | 27 MHz 3.3V VCXO for Set-Top Box Applications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CV855-02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 2.5V. 200 MHz. 5 Output SSTL-2 Zero Delay Clock Driver |
| PI6CV855-02(L) | 制造商:PERIC 功能描述: |
| PI6CV855-02L | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 75MHz to 200MHz 28-Pin TSSOP |
| PI6CV855-02LE | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV855-02LEX | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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