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參數(shù)資料
| 型號： | PI6C9911-2I |
| 英文描述： | Eight Distributed-Output Clock Driver |
| 中文描述： | 八分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大小： | 655K |
| 代理商： | PI6C9911-2I |
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PS8448A 10/10/00
PI6C991
5V High Speed Programmable Skew
Clock Buffer -
SuperClock
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C991 to
operate as explained briefly above (for testing purposes, any of the
three-level inputs can have a removable jumper to ground, or be
tied LOW through a 100
resistor. This will allow an external tester
to change the state of these pins).
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and in-
put levels supplied to REF will directly control all outputs.
Relative output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Maximum Ratings
(Above which the useful life may be impaired)
Storage Temperature ............................................65oC to +150oC
Ambient Temperature
with Power Applied..............................................55oC to +125oC
Supply Voltage to Ground Potential ....................... 0.5V to +7.0V
DC Input Voltage.................................................... 0.5V to +7.0V
Output Current into Outputs (LOW) ...................................64mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .................................>2001V
Latch-Up Current............................................................>200mA
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Operating Range
Notes for Tables on Pages 3 through 7:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connections to GND, and MID indicates an open
connection. Internal termination circuitry holds an unconnected input to V
CC
/2.
2. The level to be set on FS is determined by the normal operating frequency (f
NOM
) of the V
CO
and the Time Unit Generator (see Logic
Block Diagram). Nominal frequency (f
NOM
) always appears at 1Q0 and the other outputs when they are operated in their undivided
modes (see Table 2). The frequency appearing at the REF and FB inputs will be f
NOM
when
the output connected to FB is undivided.
The frequency of the REF and FB inputs will be f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency multiplication by
using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until V
CC
has reached 2.8V.
4. FB connected to an output selected for zero skew (ie., xF1 = xF0 = MID).
6. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal
termination resistors holds unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch
and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
7. The part should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
11. Test measurement levels are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as
shown in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. Skew is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected
when all are loaded with 30pF and terminated with 50
to 2.06V.
14. t
SKEWPR
is defined as the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
15. t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not shifted.
16. C
L
= 0pF. For C
L
= 30pF, t
SKEW0
= 0.35ns
17. There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
18. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
ambient temperature, air flow, etc.).
19. t
ODCV
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
20. t
PWH
is measured at 2.0V. t
PWL
is measured at 0.8V.
21. t
ORISE
and t
OFALL
measured between 0.8V and 2.0V.
22. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI6C9911-5 | Eight Distributed-Output Clock Driver |
| PI6C9911E | Eight Distributed-Output Clock Driver |
| PI6C9911E-2I | 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
| PI6C9911E-5I | 16-Bit Rail-to-Rail Micropower DACs in SO-8 Package; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| PI6C991-2 | Clock IC | 250ps Accuracy. 5V. TTL. 3.75 to 80 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C9911-2J | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:5V High-Speed Programmable Skew Clock Buffers |
| PI6C9911-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| PI6C9911-5I | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Clock IC | 500ps Accuracy. 5V. TTL. 3.75 to 100 MHz. Industrial Temp. Operation |
| PI6C9911-5IJ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:5V High-Speed Programmable Skew Clock Buffers |
| PI6C9911-5J | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:5V High-Speed Programmable Skew Clock Buffers |
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