![](http://datasheet.mmic.net.cn/260000/PI6C991_datasheet_15939851/PI6C991_1.png)
1
PS8448A 10/10/00
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3
3
V
F
V
2
2
3
F
V
R
G
T
2
29
28
27
26
25
24
23
22
21
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
4
3
2
1
32
31
30
Product Features
Four pairs of programmable skew outputs
3.75 to 80 MHz output operation
User-selectable output functions:
Selectable skews
Inverted and noninverted
Operation at and input frequency
Operation at 2X and 4X input frequency
Low skew <100ps typical, same pair. 250ps max.
Allow REF clock input to have Spread Spectrum
modulation for EMI reduction
2X, 4X, and outputs
3-level inputs for skew and output frequency control
External feedback, internal loop filter
Low cycle-to-cycle Jitter: <25ps RMS
Duty cycle of output clock signals: 45% min. 55% max.
Compatible with Pentium based processor
Same pinout as Cypress CY7B991
Packaged in Plastic 32-pin PLCC Package
Description
The PI6C991 is a low-skew, low jitter, 5V phase-lock loop (PLL)
programmable skew clock driver, for high performance comput-
ing and networking applications. This part offers user selectable
skew-control of 4 output pairs, providing the timing delays neces-
sary to optimize high performance clock distribution circuits.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments are determined by the input clock
frequency and the configurations selected by the user.
The PI6C991 allows the REF clock input to have Spread Spectrum
modulation for EMI reduction.
The PI6C991 is pin-compatible with Cypress RoboClock CY7B991,
with improved AC/DC characteristics.
Logic Block Diagram
Pin Configuration
32-Pin
J
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Skew Clock Buffer -
SuperClock
Vco and
Time Unit
Generator
Filter
Phase
Freq
Det
TEST
FS
FB
REF
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
Three Level
Select Inputs
SKEW
SELECT
MATRIX
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1