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參數(shù)資料
| 型號(hào)： | PI6C671FV |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | Clock Generator for Pentium Modules |
| 中文描述： | 奔騰時(shí)鐘發(fā)生器模塊 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 199K |
| 代理商： | PI6C671FV |
394
PS8137A 03/15/99
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PI6C671F
Clock Generator for Pentium Modules
Power Management Functions
Any or all clocks can be enabled or shut down via the I
2
C control
interface. All clocks stop in the LOW state. CPU, SDRAM, and PCI
clocks wait for one rising edge of PCICLK_F followed by a falling
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The I
2
C interface permits individual enable/disable of each
clock output and test mode enable.
The PI6C671F is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
During normal data transfers SDATA changes only when SDCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SDCLK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SDCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C671F generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts the
following data bytes until another start or stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
The I
2
C interface is disabled when the PWR_DWN# pin is LOW.
Preset control register contents are retained.
I
2
C Serial Configuration
Byte 0: Functional and Frequency Select
Clock Register (1 = enable, 0 = disable)
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2-Wire I
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C Control
edge of the clock of interest before settling in the LOW state. To
reduce power consumption the PI6C671F clocks may be disabled in
accordance with the following table.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C673FA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| PI6C9107U-05P9 | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C9107U-05W9 | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C9108-05P9 | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI6C9155U-01P9 | 制造商:Pericom Semiconductor Corporation 功能描述: |
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