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參數(shù)資料
| 型號： | PI6C484321FBE |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 260MHz Crystal-to-3.3V Differential LVPECL Frequency Synthesizer |
| 中文描述： | 260MHz水晶至3.3V的差分LVPECL頻率合成器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 273K |
| 代理商： | PI6C484321FBE |
3
PS8765A 08/01/05
PI6C484321
260MHz Crystal-to-3.3V Differential
LVPECL Frequency Synthesizer
Pin Description
Number
1
2, 3, 4, 28,
29, 30, 31,
32
Name
M5
Type
Description
Input
Pullup
M divider input. Data latched on LOW-to-HIGH transition of nP_
LOAD input. LVCMOS / LVTTL interface levels
M6, M7, M8,
M0, M1, M2,
M3, M4
Input
Pulldown
5, 6
N0, N1
Input
Pulldown
Determines N output divider value as defined in Table 3C Function
table. LVCMOS / LVTTL interface levels
No connect
Negative supply pins
Test output. ACTIVE in the serial mode of operation. Output driven
LOW in parallel mode. LVCMOS interface levels
Positive supply pin
7
nc
V
EE
unused
Power
8, 16
9
TEST
Output
10
V
CC
FOUT1,
nFOUT2
V
CCO
FOUT0,
nFOUT0
Power
11, 12
Output
Differential output for the synthesizer. LVPECL interface levels
13
Power
Output supply pin
14, 15
Output
Differential output for the synthesizer. LVPECL interface levels
17
MR
Input
Pulldown
Active High Master reset. When logic HIGH, the internal dividers are
reset causing the true outputs FOUTx to go low and the inverted out-
puts nFOUTx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Assertion of MR does not affect loaded M, N,
and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register on
the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shirft register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
Control transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels
Analog supply pin
Selects between crystals or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels.
Test clock input. LVCMOS / LVTTL interface levels
Crystal oscillator inputs
Parallel load input to determine when data present at M8:M0 is loaded
into M divider, and when data is present at N1:N0 sets the N output
divider value. LVCMOS / LVTTL interface levels.
Controls the clock synthesizer to be in PLL or bypass mode.
LVCMOS /LVTTL interface levels
18
S_CLOCK
Input
Pulldown
19
S_DATA
Input
Pulldown
20
S_LOAD
Input
Pulldown
21
V
CCA
Power
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
XTAL1, XTAL2
Input
Input
Pulldown
24, 25
26
nP_LOAD
Input
Pulldown
27
VCO_SEL
Input
Pullup
Notes
1.
Pullup and Pulldown refer to internal input resistors. See Pin characterstics Table for typical values.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C4853111 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux |
| PI6C4853111FAE | 功能描述:時鐘緩沖器 0.25um1P4M 2.5/3.3V Salicid RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PI6C4853111FAEX | 功能描述:時鐘緩沖器 0.25um1P4M 2.5/3.3V Salicid RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PI6C485311WE | 功能描述:時鐘緩沖器 3.3V Low Skew 1:2 Diff RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| PI6C485311WEX | 功能描述:時鐘緩沖器 3.3V Low Skew 1:2 Diff RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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