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參數(shù)資料
| 型號(hào)： | PI6C3Q993-2Q |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3.3V Programmable Skew PLL Clock Driver |
| 中文描述： | 3.3V的可編程偏移PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 544K |
| 代理商： | PI6C3Q993-2Q |
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PI6C3Q991, PI6CQ3993
8
PS8449A 10/09/00
t
REF
t
RPWH
t
ODCV
t
SKEWPR
t
SKEW0, 1
t
SKEW3,4
t
SKEW3,4
t
SKEW3,4
t
SKEW2,4
t
SKEW1,3,4
t
SKEWPR
t
SKEW0, 1
t
PD
t
ODCV
t
RPWL
t
JR
REF
FB
Q
Other Q
Inverted Q
REF Divided by 2
REF Divided by 4
t
SKEW2
t
SKEW2
l
b
m
y
S
n
o
D
.
M
.
a
M
s
U
t
R
t
F
V
0
o
V
8
,
m
i
d
n
a
e
p
n
m
u
m
i
a
M
0
1
V
/
t
C
W
P
W
O
L
r
H
G
I
H
,
p
k
c
o
t
p
n
3
s
D
H
e
c
y
d
t
p
n
0
1
0
9
%
Table 12. Input Timing Requirements
Notes:
1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D
H
is
less than t
PWC
limit, t
PWC
limit applies.
AC Timing Diagram
Notes:
V
CCQ
/PE: The AC timing diagram above applies to V
CCQ
/PE=V
CC
. For V
CCQ
/PE=GND, the negative edge of FB aligns with the negative edge of REF,
divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are
loaded with 20pF and terminated with 75Ohm to V
CC
/2.
t
SKEWPR
: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t
U
.
t
SKEW0
:
The skew between outputs when they are selected for 0t U.
t
DEV
:
The output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
t
ODCV
:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
t
LOCK
:
The time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
t
PWH
is measured at 2.0V.
t
PWL
is measured at 0.8V.
t
ORISE
and t
OFALL
are measured between 0.8V and 2.0V.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PI6C3Q993-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| PI6C3Q993-5I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Clock IC | 500ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz. Industrial Temp. Operation |
| PI6C3Q993-5IQ | 制造商:Pericom Semiconductor Corporation 功能描述:Programmable PLL Clock Driver Single 28-Pin QSOP |
| PI6C3Q993-5IQX | 制造商:Pericom Semiconductor Corporation 功能描述:Programmable PLL Clock Driver Single 28-Pin QSOP T/R |
| PI6C3Q993-5Q | 制造商:Pericom Semiconductor Corporation 功能描述:Programmable PLL Clock Driver Single 28-Pin QSOP |
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