參數(shù)資料
型號(hào): PI6C180V
英文描述: Eighteen Distributed-Output Clock Driver
中文描述: 18分布式輸出時(shí)鐘驅(qū)動(dòng)器
文件頁數(shù): 10/12頁
文件大小: 580K
代理商: PI6C180V
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P8399-1 06/11/99
PI6C102-16
Spread Spectrum Clock Synthesizer
for Mobile Pentium II
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Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load for each type of output buffer.
2. Minimum rise/fall times are guaranteed at minimum specified load for each type of output buffer.
3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an
additional 500
resistor in parallel.
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Minimum and Maximum Expected Capacitive Loads
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall time
are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
CPUCLK
PCICLK
REF
32
33
22
/33
2
6
CL
CL
CL
PI6C102-16
1 Device load
Meets PCI2.1 Req.
1 Device load
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