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參數資料
| 型號： | PI6C106-H |
| 英文描述： | CPU System Clock Generator |
| 中文描述： | CPU系統(tǒng)時鐘發(fā)生器 |
| 文件頁數： | 4/12頁 |
| 文件大小： | 580K |
| 代理商： | PI6C106-H |
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P8399-1 06/11/99
PI6C102-16
Spread Spectrum Clock Synthesizer
for Mobile Pentium II
Notes:
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PWR_DWN# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66MHz. Similar operation as CPU = 100 MHz.
PCI_STOP# is an input signal used to turn off PCI clocks for low
power operation. PCI clocks are stopped in the LOW state and
PCI_STOP# Timing Diagram
PWR_DWN# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
CPUCLK
(Internal)
PCICLK
(Internal)
VCO
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
Crystal
Notes:
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operation as CPU = 100 MHz.
started with a guaranteed full high pulse width. There is ONLY one
rising edge of external PCICLK after the clock control logic
.
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